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TNETV2840ENGGU 数据表(PDF) 74 Page - Texas Instruments |
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TNETV2840ENGGU 数据表(HTML) 74 Page - Texas Instruments |
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74 / 91 page ![]() Electrical Specifications 74 December 1999 − Revised October 2008 SPRS122F Table 5−10. McBSP0/1/2 T ransmit and Receive Switching Characteristics† PARAMETER MIN MAX UNIT td(BCKXH-BFXV) Delay time, x_BCLKX high to internal x_BFSX valid BCLKX ext 2 15 ns tdis(BCKXH-BDXHZ) Disable time, x_BCLKX high to x_BDX high impedance following last data bit BCLKX ext 1 18 ns Delay time, x_BCLKX high to x_BDX valid. This applies to all bits except the first bit transmitted. BCLKX ext 4 20 td(BCKXH-BDXV) Delay time, x_BCLKX high to x_BDX valid.‡ Only applies to first bit transmitted when in Data Delay 1 DXENA = 0 BCLKX ext 16 ns Only applies to first bit transmitted when in Data Delay 1 or 2 (XDATDLY=01b or 10b) modes DXENA = 1 BCLKX ext 4H+19 ten(BCKXH-BDX) Enable time, x_BCLKX high to x_BDX driven.‡ Only applies to first bit transmitted when in Data Delay 1 DXENA = 0 BCLKX ext 2 ns ten(BCKXH-BDX) Only applies to first bit transmitted when in Data Delay 1 or 2 (XDATDLY=01b or 10b) modes DXENA = 1 BCLKX ext 4H+2 ns td(BFXH-BDXV) Delay time, x_BFSX high to x_BDX valid.‡ Only applies to first bit transmitted when in Data Delay 0 DXENA = 0 BFSX ext 17 ns td(BFXH-BDXV) Only applies to first bit transmitted when in Data Delay 0 (XDATDLY=00b) mode. DXENA = 1 BFSX ext 4H+15 ns ten(BFXH-BDX) Enable time, x_BFSX high to x_BDX driven.‡ Only applies to first bit transmitted when in Data Delay 0 DXENA = 0 BFSX ext 1 ns ten(BFXH-BDX) Only applies to first bit transmitted when in Data Delay 0 (XDATDLY=00b) mode DXENA = 1 BFSX ext 4H+5 ns † Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. ‡ See the TMS320C54x DSP Reference Set, Volume 5: Enhanced Peripherals (literature number SPRU302) for a description of the DX enable (DXENA) and data delay features of the McBSP. |
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