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PC87309VLJ 数据表(PDF) 23 Page - National Semiconductor (TI) |
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PC87309VLJ 数据表(HTML) 23 Page - National Semiconductor (TI) |
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23 / 192 page ![]() Configuration 23 www.national.com TABLE 2-5. Plug and Play (PnP) Logical Device Control Registers TABLE 2-6. Plug and Play (PnP) I/O Space Configuration Registers Index Name Definition 0030h Activate For each logical device there is one Activate register that controls whether or not the logical device is active on the ISA bus. This is a read/write register. Before a logical device is activated, I/O Range Check must be disabled. Bit 0 - Logical Device Activation Control 0: Do not activate the logical device. 1: Activate the logical device. Bits 7-1 - Reserved These bits are reserved and return 0 on reads. 0031h I/O Range Check This register is used to perform a conflict check on the I/O port range programmed for use by a logical device. This register is read/write. Bit 0 - I/O Range Check control 0: The logical device drives 00AAh. 1: The logical device responds to I/O reads of the logical device's assigned I/O range with a 0055h when I/O Range Check is enabled. Bit 1 - Enable I/O Range Check 0: I/O Range Check is disabled. 1: I/O Range Check is enabled. (I/O Range Check is valid only when the logical device is inactive). Bits 7-2 - Reserved These bits are reserved and return 0 on reads. Index Name Definition 60h I/O Port Base Address Bits (15-8) Descriptor 0 Read/write value indicating the selected I/O lower limit address bits 15-8 for I/O descriptor 0. Bits 7-3 (for A15-11) are read only 00000b. 61h I/O Port Base Address Bits (7-0) Descriptor 0 Read/write value indicating the selected I/O lower limit address bits 7-0 for I/O descriptor 0. 62h I/O Port Base Address Bits (15-8) Descriptor 1 Read/write value indicating the selected I/O lower limit address bits 15-8 for I/O descriptor 1. Bits 7-3 (for A15-11) are ready only 00000b. 63h I/O Port Base Address Bits (7-0) Descriptor 1 Read/write value indicating the selected I/O lower limit address bits 7-0 for I/O descriptor 1. |
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