PC87309VLJ datasheet(95/192 Pages) NSC

95 / 192 page

Parallel Port (Logical Device 1)

www.national.com

Once DRQ is asserted, it is held asserted for four DMA

transfers, as long as the FIFO is able to process these

four transfers, i.e., FIFO not empty backward.

When these four transfers are done, the DRQ behaves

as follows:

— If DMA fairness prevents DRQ assertion (as in the

case of 32 consecutive DMA transfers) then DRQ

becomes low.

— If the FIFO is not able to process another four trans-

fers (below threshold), then DRQ is becomes low.

— If the FIFO is able to process another four transfers

(still above the threshold and no fairness to prevent

DRQ assertion), then DRQ is held asserted as de-

tailed above.

The flush time-out is an 8-bit counter that counts 256

clocks of 24 MHz and triggers DRQ assertion when the

terminal-count is reached, i.e., when flush time-out ex-

pires). The counter is enabled for counting backward

when the peripheral state machine writes a byte and

DRQ is not asserted. Once enabled, it counts the 24

MHz clocks. The counter is reset and disabled when

DRQ is asserted. The counter is also reset and disabled

for counting forward and when demand the DMA is dis-

abled.

This mechanism is reset whenever ECP mode is

changed, the same way the FIFO is flushed in this case.

0: Disabled.

1: Enabled.

Bit 7 - Bit 3 of CNFGA

This bit may be utilized by the user. The value of this bit

is reflected on bit 3 of the ECP CNFGA register.

4.6

DETAILED ECP MODE DESCRIPTIONS

TABLE 4-11 "ECP Modes" on page 96 summarizes the func-

tionality of the ECP in each mode. The following Sections de-

scribe how the ECP functions in each mode, in detail.

4.6.1

Software Controlled Data Transfer (Modes 000

and 001)

Software controlled data transfer is supported in modes 000

and 001. The software generates peripheral-device cycles

by modifying the DATAR and DCR registers and reading

the DSR, DCR and DATAR registers. The negotiation

phase and nibble mode transfer, as defined in the IEEE

1284 standard, are performed in these modes.

In these modes the FIFO is reset (empty) and is not func-

tional, the DMA and RLE are idle.

Mode 000 is for the forward direction only; the direction bit

(bit 5 of DCR) is forced to 0 and PD7-0 are driven. Mode 001

is for both the forward and backward directions. The direc-

tion bit controls whether or not pins PD7-0 are driven.

4.6.2

Automatic Data Transfer (Modes 010 and 011)

Automatic data transfer (ECP cycles generated by hard-

ware) is supported only in modes 010 and 011 (Parallel Port

and ECP FIFO modes). Automatic DMA access to fill or

empty the FIFO is supported in modes 010, 011 and 110.

Mode 010 is for the forward direction only; the direction bit

is forced to 0 and PD7-0 are driven. Mode 011 is for both

the forward and backward directions. The direction bit con-

trols whether PD7-0 are driven.

Automatic Run Length Expanding (RLE) is supported in the

backward direction.

Forward Direction (Bit 5 of DCR = 0)

When the ECP is in forward direction and the FIFO is not full

(bit 1 of ECR is 0) the FIFO can be filled by software writes

to the FIFO registers (AFIFO and DFIFO in mode 011, and

CFIFO in mode 010).

When DMA is enabled (bit 3 of ECR is 1 and bit 2 of ECR is

0) the ECP automatically issues DMA requests to fill the

FIFO with data bytes (not including command bytes).

When the ECP is in forward direction and the FIFO is not

empty (bit 0 of ECR is 0) the ECP pops a byte from the FIFO

and issues a write signal to the peripheral device. The ECP

drives AFD according to the operation mode (bits 7-5 of

ECR) and according to the tag of the popped byte as fol-

lows:

In Parallel Port FIFO mode (mode 010) AFD is con-

trolled by bit 1 of DCR.

In ECP mode (mode 011) AFD is controlled by the

popped tag. AFD is driven high for normal data bytes

and driven low for command bytes.

ECP (Forward) Write Cycle

An ECP write cycle starts when the ECP drives the popped

tag onto AFD and the popped byte onto PD7-0. When

BUSY is low the ECP asserts STB. In 010 mode the ECP

deactivates STB to terminate the write cycle. In 011 mode

the ECP waits for BUSY to be high.

When BUSY is high, the ECP deactivates STB, and chang-

es AFD and PD7-0 only after BUSY is low.

PC87309VLJ 数据表(PDF) 95 Page - National Semiconductor (TI)

PC87309VLJ 数据表(HTML) 95 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载