PC87309VLJ datasheet(45/192 Pages) NSC

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The Floppy Disk Controller (FDC) (Logical Device 0)

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1: The data transfer rate is low, i.e., 300 Kbps or 250 Kbps.

Bits 2,1 - Data Rate Select 1,0 (DRATE1,0)

(PS/2 Drive Mode Only)

In PC-AT drive mode, these bits are reserved, in TRI-

STATE and used by the status register of the hard disk.

In PS/2 drive mode, these bits indicate the status of the

DRATE1,0 bits programmed in DSR or CCR, whichever

is written last.

The significance of each value for these bits depends on

the supported speeds. See TABLE 3-5 on page 43.

00: Data transfer rate is 500 Kbps.

01: Data transfer rate is 300 Kbps.

10: Data transfer rate is 250 Kbps.

11: Data transfer rate is 1 Mbps.

Bits 6-3 - Reserved

These bits are reserved and are always 1. In PC-AT

mode these bits are also in TRI-STATE. They are used

by the status register of the fixed hard disk.

Bit 7 - Disk Changed (DSKCHG)

This bit reflects the status of the DSKCHG disk interface

input signal.

During power down this bit is invalid, if it is read by the

software.

0: DSKCHG is not active.

1: DSKCHG is active.

3.3.9

Configuration Control Register (CCR)

This write-only register can be used to set the data transfer

rate (in place of the DSR) for PC-AT, PS/2 and MicroChan-

nel applications. Other applications can set the data trans-

fer rate in the DSR. See Section 3.3.6 on page 43.

This register is not affected by a software reset.

The data rate of the floppy controller is determined by the

last write to either the CCR register or to the DSR register.

Bits 1,0 - Data Transfer Rate Select 1,0 (DRATE 1,0)

These bits determine the data transfer rate for the Flop-

py Disk Controller (FDC), depending on the supported

speeds.

TABLE 3-5 on page 43 shows the data transfer rate se-

lected by each value of this field.

These bits are unaffected by a software reset, and are

set to 10 (250 Kbps) after a hardware reset.

Bits 7-2 - Reserved

These bits should be set to 0.

3.4

THE PHASES OF FDC COMMANDS

FDC commands may be in the command phase, the execu-

tion phase or the result phase. The active phase determines

how data is transferred between the Floppy Disk Controller

(FDC) and the host microprocessor. When no command is

in progress, the FDC may be either idle or polling a drive.

3.4.1

Command Phase

During the command phase, the microprocessor writes a

series of bytes to the Data Register (FIFO). The first com-

mand byte contains the opcode for the command, which the

controller can interpret to determine how many more com-

mand bytes to expect. The remaining command bytes con-

tain the parameters required for the command.

The number of command bytes varies for each command.

All command bytes must be written in the order specified in

the Command Description Table in Section 3.7 on page 53.

The execution phase starts immediately after the last byte

in the command phase is written.

Prior to performing the command phase, the Digital Output

set with the Data rate Select Register (DSR) or the Config-

uration Control Register (CCR).

The Main Status Register (MSR) controls the flow of com-

mand bytes, and must be polled by the software before writ-

ing each command phase byte to the Data Register (FIFO).

Prior to writing a command byte, bit 7 of MSR (RQM, Re-

quest for Master) must be set and bit 6 of MSR (DIO, Data

I/O direction) must be cleared.

After the first command byte is written to the Data Register

(FIFO), bit 4 of MSR (CMD PROG, Command in Progress)

is also set and remains set until the last result phase byte is

read. If there is no result phase, the CMD PROG bit is

cleared after the last command byte is written.

A new command may be initiated after reading all the result

bytes from the previous command. If the next command re-

quires selection of a different drive or a change in the data

rate, the DOR and DSR or CCR should be updated, accord-

ingly. If the command is the last command, the software

should deselect the drive.

Normally, command processing by the controller core and

updating of the DOR, DSR, and CCR registers by the micro-

processor are operations that can occur independently of

one another. Software must ensure that the these registers

are not updated while the controller is processing a com-

mand.

3.4.2

Execution Phase

During the execution phase, the Floppy Disk Controller

(FDC) performs the desired command.

Commands that involve data transfers (e.g., read, write and

format operations) require the microprocessor to write or

read data to or from the Data Register (FIFO) at this time.

Some commands, such as SEEK or RECALIBRATE, con-

trol the read/write head movement on the disk drive during

the execution phase via the disk interface signals. Execu-

tion of other commands does not involve any action by the

microprocessor or disk drive, and consists of an internal op-

eration by the controller.

76543210

Reset

Required

Configuration Control

Offset 07h

Reserved

DRATE1

DRATE0

Write Operations

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