PC87309VLJ datasheet(19/192 Pages) NSC

19 / 192 page

Configuration

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2.0

Conﬁguration

The PC87309VLJ is partially configured by hardware, dur-

ing reset. The configuration can also be changed by soft-

ware, by changing the values of the configuration registers.

The configuration registers are accessed using an Index

ping options define the addresses of the configuration reg-

isters. See Section 2.1.2 "The Index and Data Register

Pair".

After the Index and Data register pair have determined the

addresses of the conﬁguration registers, the addresses of

the Index and Data registers can be changed within the ISA

I/O address space, and a 11-bit programmable register con-

trols references to their addresses and to the addresses of

the other registers.

This chapter describes the hardware and software configu-

ration processes. For each, it describes configuration of the

Index and Data register pair first. See Sections 2.1 "HARD-

WARE CONFIGURATION" and 2.2 "SOFTWARE CON-

FIGURATION" on page 20.

Section 2.3 "THE CONFIGURATION REGISTERS" on

page 21 presents an overview of the configuration registers

of the PC87309VLJ and describes each in detail.

2.1

HARDWARE CONFIGURATION

The PC87309VLJ Hardware Cofiguration is based on three

strap-pins: BADDR0, BADDR1 and CFG0.

The PC87309VLJ wakes up with the KBC active (enabled)

and all the other logical devices wake up inactive (disabled).

This is always true and is not affected by strapping.

Clock source is 48MHz, fed via CLKIN.

2.1.1

Wake Up Options

The PC87309VLJ supports three available Wake Up Op-

tions:

Full PnP ISA with Full-IR mode.

PnP Motherboard with Full-IR mode.

PnP Motherboard with Two-UART mode.

TABLE 2-1 "Strap Pins and Base Addresses" on page 20

shows the strap pins and their applicable wake up options.

The three available wake up options are a combination of

the four basic modes which are determined by three strap-

pins during reset:

BADDR0 and BADDR1 strap-pins select one of two basic

modes.

Full PnP ISA mode – System wakes up in Wait for Key

state. (Not available when in Two-UART mode - see

CFG0 in TABLE 2-1).

Index and Data register addresses are as defined in the

“Plug and Play ISA Specification, Version 1.0a, May 5,

1994.”

PnP Motherboard mode – system wakes up in Conﬁg

state.

The BIOS configures the PC87309VLJ. Index and Data

the PnP Index and Data registers. Configuration regis-

ters can be accessed as if the serial isolation procedure

had already been done, and the PC87309VLJ is select-

ed.

The BIOS may switch the addresses of the Index and

Data registers to the PnP ISA addresses of the Index

and Data registers, by using software to modify the base

address bits, as shown in Section 2.4.3 on page 29.

CFG0 strap-pin selects between the following two modes:

Mode 1: Full-IR Mode

UART1 works as UART; UART2 works as fully IR-

compliant device

Mode 2: Two-UART Mode

Either both UART1 and UART2 work as UARTs, or

UART 1 works as UART and UART2 works as partially

IR-compliant device, providing only IRRX and IRTX

support

2.1.2

The Index and Data Register Pair

During reset, a hardware strapping option on the BADDR0

and BADDR1 pins defines an address for the Index and

Data Register pair.

TABLE 2-1 "Strap Pins and Base Addresses" shows the

base addresses for the Index and Data registers that hard-

ware sets for each combination of values of the Base Ad-

dress strap pins (BADDR0 and BADDR1). You can access

and change the content of the configuration registers at any

time, as long as the base addresses of the Index and Data

registers are defined.

When BADDR1 is low (0), the PnP protocol defines the ad-

dresses of the Index and Data register, and the system

wakes up from reset in the Wait for Key state.

When BADDR1 is high (1), the addresses of the Index and

Data register are according to TABLE 2-1 "Strap Pins and

Base Addresses", and the system wakes up from reset in

the Config state.

This configures the PC87309VLJ with default values, auto-

matically, without software intervention. After reset, use

software as described in Section 2.2 "SOFTWARE CON-

FIGURATION" on page 20 to modify the selected base ad-

dress of the Index and Data register pair, and the defaults

for configuration registers.

The PnP soft reset has no effect on the logical devices, ex-

cept for the effect of the Activate registers (index 30h) in

each logical device.

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