PC87309VLJ datasheet(91/192 Pages) NSC

91 / 192 page

Parallel Port (Logical Device 1)

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4.5.11

Configuration Register B (CNFGB)

Configuration register B (CNFGB) is read only. Reading this

and DMA channel, and the state of the interrupt line.

Writing to this register has no effect and the data is ignored.

Bits 1,0 - DMA Channel Select

These bits reflect the value of bits 1,0 of the PP Config0

tocol and ISA Interface Standard defines these bits as

shown in TABLE 4-7 "ECP Mode DMA Selection".

Bits 1,0 of PP Config0 are read/write bits, but CNFGB

bits are read only.

Upon reset, these bits are initialized to 00.

TABLE 4-7. ECP Mode DMA Selection

Bit 2 - Reserved

This bit is reserved and is always 0.

Bits 5-3 - Interrupt Select Bits

These bits reflect the value of bits 5-3 of the PP Config0

tocol and ISA Interface Standard defines these bits as

shown in TABLE 4-8 "ECP Mode Interrupt Selection".

Bits 5-3 of PP Config0 are read/write bits, but CNFGB

bits are read only.

Upon reset, these bits have undefined values.

TABLE 4-8. ECP Mode Interrupt Selection

Bit 6 - IRQ Signal Value

This bit holds the value of the IRQ signal configured by

the Interrupt Select register (index 70h of this logical de-

vice).

Bit 7 - Reserved

This bit is reserved and is always 0.

4.5.12

Extended Control Register (ECR)

This register controls the ECP and parallel port functions. On

reset this register is initialized to 00010xx1 (bits 1 and 2 de-

pend on the clock status). IOCHRDY is driven low on an ECR

read when the ECR status bits do not hold updated data.

Bit 0 - FIFO Empty

This bit continuously reflects the FIFO state, and there-

fore can only be read. Data written to this bit is ignored.

When the ECP clock is frozen this bit is read as 1, re-

gardless of the actual FIFO state.

0: The FIFO has at least one byte of data.

1: The FIFO is empty or ECP clock is frozen.

Bit 1 - FIFO Full

This bit continuously reflects the FIFO state, and there-

fore can only be read. Data written to this bit is ignored.

When the ECP clock is frozen this bit is read as 1, re-

gardless of the actual FIFO state.

0: The FIFO has at least one free byte.

1: The FIFO is full or ECP clock frozen.

Bit 1 Bit 0

DMA Conﬁguration

8-bit DMA selected by jumpers. (Default)

DMA channel 1 selected.

DMA channel 2 selected.

DMA channel 3 selected.

76543210

Reset

Required

Configuration Register B

(CNFGB)

Offset 401h

Reserved

Interrupt Select

IRQ Signal Value

Reserved

DMA Channel Select

Bits 7-5 of ECR = 111

Bit 5

Bit 4

Bit 3

Interrupt Selection

Selected by jumpers.

IRQ7 selected.

IRQ9 selected.

IRQ10 selected.

IRQ11 selected.

IRQ14 selected.

IRQ15 selected.

IRQ5 selected.

76543210

Reset

Required

Extended Control

Offset 402h

ECP Interrupt Service

ECP Interrupt Mask

ECP Mode Control

ECP DMA Enable

FIFO Full

FIFO Empty

PC87309VLJ 数据表(PDF) 91 Page - National Semiconductor (TI)

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