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PC87309VLJ 数据表(PDF) 87 Page - National Semiconductor (TI) |
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PC87309VLJ 数据表(HTML) 87 Page - National Semiconductor (TI) |
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87 / 192 page  Parallel Port (Logical Device 1) 87 www.national.com 4.4.3 Hardware Operation The ECP uses an internal clock, which can be frozen to re- duce power consumption during power down. In this power- down state the DMA is disabled, all interrupts (except ACK) are masked, and the FIFO registers are not accessible (ac- cess is ignored). The other ECP registers are unaffected by power-down and are always accessible when the ECP is enabled. During power-down the FIFO status and contents become inaccessible, and the system reads bit 2 of ECR as 0, bit 1 of ECR as 1 and bit 0 of ECR as 1, regardless of the actual values of these bits. The FIFO status and contents are not lost, however, and when the clock activity resumes, the values of these bits resume their designated functions. When the clock is frozen, an on-going ECP cycle may be corrupted, but the next ECP cycle will not start even if the FIFO is not empty in the forward direction, or not full in the backward direction. If the ECP clock starts or stops toggling during a system cycle that accesses the FIFO, the cycle may yield wrong data. ECP output signals are inactive when the ECP is disabled. Only the FIFO, DMA and RLE do not function when the clock is frozen. All other registers are accessible and func- tional. The FIFO, DMA and RLE are affected by ECR mod- ifications, i.e., they are reset when exits from modes 010 or 011 are carried out even while the clock is frozen. 4.5 ECP MODE REGISTERS The ECP registers are each a byte wide, and are listed in TABLE Table 4-6 in order of their offsets from the base ad- dress of the parallel port. In addition, the ECP has control registers at second level offsets, that are accessed via the EIR and EDR registers. See 4.5.2 "Second Level Offsets" on page 88. TABLE 4-6. Extended Capabilities Parallel Port (ECP) Registers 4.5.1 Accessing the ECP Registers The AFIFO, CFIFO, DFIFO and TFIFO registers access the same ECP FIFO. The FIFO is accessed at Base + 000h, or Base + 400h, depending on the mode field of ECR and the register. The FIFO can be accessed by system DMA cycles, as well as system PIO cycles. When the DMA is configured and enabled (bit 3 of ECR is 1 and bit 2 of ECR is 0) the ECP automatically (by hardware) issues DMA requests to fill the FIFO (in the forward direc- tion when bit 5 of DCR is 0) or to empty the FIFO (in the backward direction when bit 5 of DCR is 1). All DMA trans- fers are to or from these registers. The ECP does not assert DMA requests for more than 32 consecutive DMA cycles. The ECP stops requesting the DMA when TC is detected during an ECP DMA cycle. Offset Symbol Description Modes (ECR Bits) 7 6 5 R/W 000h DATAR Parallel Port Data Register 0 0 0 0 0 1 R/W 000h AFIFO ECP Address FIFO 0 1 1 W 001h DSR Status Register All Modes R 002h DCR Control Register All Modes R/W 400h CFIFO Parallel Port Data FIFO 0 1 0 W 400h DFIFO ECP Data FIFO 0 1 1 R/W 400h TFIFO Test FIFO 1 1 0 R/W 400h CNFGA Configuration Reg- ister A 1 1 1 R 401h CNFGB Configuration Reg- ister B 1 1 1 R 402h ECR Extended Control Register All Modes R/W 403h EIR Extended Index Register All Modes R/W 404h EDR Extended Data Register All Modes R/W 405h EAR Extended Auxiliary Status Register All Modes R/W Control Registers at Second Level Offsets 00h Control0 All Modes R/W 02h Control2 All Modes R/W 04h Control4 All Modes R/W 05h PP Confg0 All Modes R/W |
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