PC87309VLJ datasheet(85/192 Pages) NSC

85 / 192 page

Parallel Port (Logical Device 1)

www.national.com

4.3.10

EPP Mode Transfer Operations

The EPP transfer operations are address read or write, and

data read or write. An EPP transfer is composed of a sys-

tem read or write cycle from or to an EPP register, and an

EPP read or write cycle from a peripheral device to an EPP

EPP 1.7 Address Write

The following procedure selects a peripheral device or reg-

ister as illustrated in FIGURE FIGURE 4-1 "EPP 1.7 Ad-

dress Write".

1. The system writes a byte to the EPP Address register.

WR becomes low to latch D7-0 into the EPP Address

PD7-0 and the EPP pulls WRITE low.

2. The EPP pulls ASTRB low to indicate that data was

sent.

3. If WAIT was low during the system write cycle,

IOCHRDY becomes low. When WAIT becomes high,

the EPP pulls IOCHRDY high.

4. When IOCHRDY becomes high, it causes WR to be-

come high. If WAIT is high during the system write cycle,

then the EPP does not pull IOCHRDY to low.

5. When WR becomes high, it causes the EPP to pull first

ASTRB and then WRITE to high. The EPP can change

PD7-0 only when WRITE and ASTRB are both high.

FIGURE 4-1. EPP 1.7 Address Write

EPP 1.7 Address Read

The following procedure reads from the EPP Address reg-

ister as shown in FIGURE FIGURE 4-2 "EPP 1.7 Address

Read".

1. The system reads a byte from the EPP Address register.

RD goes low to gate PD7-0 into D7-0.

2. The EPP pulls ASTRB low to signal the peripheral to

start sending data.

3. If WAIT is low during the system read cycle. Then the

EPP pulls IOCHRDY low. When WAIT becomes high,

the EPP stops pulling IOCHRDY to low.

4. When IOCHRDY becomes high, it causes RD to be-

come high. If WAIT is high during the system read cycle

then the EPP does not pull IOCHRDY to low.

5. When RD becomes high, it causes the EPP to pull

ASTRB high. The EPP can change PD7-0 only when

ASTRB is high. After ASTRB becomes high, the EPP

puts D7-0 in TRI-STATE.

FIGURE 4-2. EPP 1.7 Address Read

EPP 1.7 Data Write and Read

This procedure writes to the selected peripheral device or

EPP 1.7 data read or write operations are similar to EPP 1.7

Address register read or write operations, except that the

data strobe (DSTRB signal), and the EPP Data register, re-

place the address strobe (ASTRB signal) and the EPP Ad-

dress register, respectively.

4.3.11

EPP 1.7 and 1.9 Data Write and Read

Operations

EPP 1.9 Address Write

The following procedure selects a peripheral or register as

shown in FIGURE FIGURE 4-3 "EPP 1.9 Address Write".

1. The system writes a byte to the EPP Address register.

2. The EPP pulls IOCHRDY low, and waits for WAIT to be-

come low.

3. When WAIT becomes low, the EPP pulls WRITE to low

and drives the latched byte onto PD7-0. If WAIT was al-

ready low, steps 2 and 3 occur concurrently.

4. The EPP pulls ASTRB low and waits for WAIT to be-

come high.

5. When WAIT becomes high, the EPP stops pulling

IOCHRDY low, and waits for WR to become high.

6. When WR becomes high, the EPP pulls ASTRB high,

and waits for WAIT to become low.

7. If no EPP write is pending when WAIT becomes low, the

EPP pulls WRITE to high. Otherwise, WRITE remains

low, and the EPP may change PD7-0.

D7-0

WAIT

ASTRB

WRITE

PD7-0

IOCHRDY

D7-0

WAIT

ASTRB

WRITE

PD7-0

IOCHRDY

PC87309VLJ 数据表(PDF) 85 Page - National Semiconductor (TI)

PC87309VLJ 数据表(HTML) 85 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载