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PC87309VLJ 数据表(PDF) 30 Page - National Semiconductor (TI) |
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PC87309VLJ 数据表(HTML) 30 Page - National Semiconductor (TI) |
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30 / 192 page  Configuration 30 www.national.com 2.5 FDC CONFIGURATION REGISTERS (LOGICAL DEVICE 0) 2.5.1 SuperI/O FDC Configuration Register This read/write register is reset by hardware to 20h. Bit 0 - TRI-STATE Control When set, this bit causes the FDC pins to be in TRI- STATE (except the IRQ and DMA pins) when the FDC is inactive (disabled). This bit is ORed with a bit of PMC1 register of Logical Device 4. 0: FDC pins are not put in TRI-STATE. 1: FDC pins are put in TRI-STATE. Bits 4-1 - Reserved Bit 5 - DENSEL Polarity Control 0: DENSEL is active low for 500 Kbps or 1 Mbps data rates. 1: DENSEL is active high for 500 Kbps or 1 Mbps data rates. (Default) Bit 6 - TDR Register Mode 0: PC-AT Compatible drive mode (bits 7 through 2 of TDR are not driven). 1: Enhanced drive mode (bits 7 through 2 of TDR are driven on TDR read). Bit 7 - Four Drive Control 0: Two floppy drives are directly controlled by DR1-0, MTR1-0. 1: Four floppy drives are controlled with the aid of an external decoder. 2.5.2 Drive ID Register This read/write register is reset by hardware to 00h. These bits control bits 5 and 4 of the enhanced TDR register. Bits 1,0 - Drive 0 ID These bits are reflected on bits 5 and 4, respectively, of the Tape Drive Register (TDR) of the FDC when drive 0 is accessed. See Section 3.3.4 "Tape Drive Register (TDR)" on page 41. Bits 3,2 - Drive 1 ID These bits are reflected on bits 5 and 4, respectively, of the TDR register of the FDC when drive 1 is accessed. See Section 3.3.4 "Tape Drive Register (TDR)" on page 41. Bits 7-4 - Reserved 2.6 SUPERI/O PARALLEL PORT CONFIGURATION REGISTER (LOGICAL DEVICE 1) This read/write register is reset by hardware to F2h. To maintain compatibility with future chips, it is recommended not to change bits 7-4 during normal operation. Before changing from any EPP mode to another mode, initialize bits 3-0 of CTR to 0100b. (See 4.2.4 on page 81.) Bit 0 - TRI-STATE Control When set, this bit causes the parallel port pins to be in TRI-STATE (except IRQ and DMA pins) when the paral- lel port is inactive (disabled). This bit is ORed with a bit of the PMC1 register of Logical Device4. TRI-STATE Control Four Drive Control 76543210 Reset Required 0 0 0 0 0 1 0 0 Super I/O FDC Index F0h Configuration Reserved Register, DENSEL Polarity Control TDR Register Mode Drive 0 ID Reserved 76543210 Reset Required 0 0 0 0 0 0 0 0 Index F1h Drive ID Register, Drive 1 ID TRI-STATE Control Parallel Port Mode Select 76543210 Reset Required 0 1 0 0 1 1 1 1 Index F0h Configuration Register, Reserved SuperI/O Parallel Port Clock Enable Reserved Configuration Bits within the Parallel Port |
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