PC87309VLJ datasheet(6/192 Pages) NSC

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Table of Contents

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3.7.23

The VERSION Command ............................................................................................ 76

3.7.24

The WRITE DATA Command ...................................................................................... 76

3.7.25

The WRITE DELETED DATA Command .................................................................... 77

3.8

EXAMPLE OF A FOUR-DRIVE CIRCUIT USING THE PC87309 ............................................. 78

4.0

Parallel Port (Logical Device 1)

4.1

PARALLEL PORT CONFIGURATION ...................................................................................... 79

4.1.1

Parallel Port Operation Modes .................................................................................... 79

4.1.2

Configuring Operation Modes ...................................................................................... 79

4.1.3

Output Pin Protection .................................................................................................. 79

4.2

STANDARD PARALLEL PORT (SPP) MODES ........................................................................ 79

4.2.1

SPP Modes Register Set ............................................................................................. 80

4.2.2

SPP Data Register (DTR) ............................................................................................ 80

4.2.3

Status Register (STR) ................................................................................................. 81

4.2.4

SPP Control Register (CTR) ........................................................................................ 81

4.3

ENHANCED PARALLEL PORT (EPP) MODES ........................................................................ 82

4.3.1

EPP Register Set ......................................................................................................... 82

4.3.2

SPP or EPP Data Register (DTR) ............................................................................... 83

4.3.3

SPP or EPP Status Register (STR) ............................................................................. 83

4.3.4

SPP or EPP Control Register (CTR) ........................................................................... 83

4.3.5

EPP Address Register (ADDR) ................................................................................... 83

4.3.6

EPP Data Register 0 (DATA0) .................................................................................... 84

4.3.7

EPP Data Register 1 (DATA1) .................................................................................... 84

4.3.8

EPP Data Register 2 (DATA2) .................................................................................... 84

4.3.9

EPP Data Register 3 (DATA3) .................................................................................... 84

4.3.10

EPP Mode Transfer Operations .................................................................................. 85

4.3.11

EPP 1.7 and 1.9 Data Write and Read Operations ..................................................... 85

4.4

EXTENDED CAPABILITIES PARALLEL PORT (ECP) ............................................................. 86

4.4.1

ECP Modes ................................................................................................................. 86

4.4.2

Software Operation ...................................................................................................... 86

4.4.3

Hardware Operation .................................................................................................... 87

4.5

ECP MODE REGISTERS .......................................................................................................... 87

4.5.1

Accessing the ECP Registers ...................................................................................... 87

4.5.2

Second Level Offsets .................................................................................................. 88

4.5.3

ECP Data Register (DATAR) ....................................................................................... 88

4.5.4

ECP Address FIFO (AFIFO) Register ......................................................................... 88

4.5.5

ECP Status Register (DSR) ......................................................................................... 88

4.5.6

ECP Control Register (DCR) ....................................................................................... 89

4.5.7

Parallel Port Data FIFO (CFIFO) Register ................................................................... 90

4.5.8

ECP Data FIFO (DFIFO) Register ............................................................................... 90

4.5.9

Test FIFO (TFIFO) Register ........................................................................................ 90

4.5.10

Configuration Register A (CNFGA) ............................................................................. 90

4.5.11

Configuration Register B (CNFGB) ............................................................................. 91

4.5.12

Extended Control Register (ECR) ............................................................................... 91

4.5.13

ECP Extended Index Register (EIR) ........................................................................... 92

4.5.14

ECP Extended Data Register (EDR) ........................................................................... 93

PC87309VLJ 数据表(PDF) 6 Page - National Semiconductor (TI)

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