PC87309VLJ datasheet(47/192 Pages) NSC

47 / 192 page

The Floppy Disk Controller (FDC) (Logical Device 0)

www.national.com

Overrun Errors

An overrun or underrun error terminates the execution of a

command, if the system does not transfer data within the al-

lotted data transfer time. (See Section 3.3.7 on page 43.

)

This puts the controller in the result phase.

During a read overrun, the microprocessor is required to

read the remaining bytes of the sector before the controller

asserts the appropriate IRQ signifying the end of execution.

During a write operation, an underrun error terminates the

execution phase after the controller has written the remain-

ing bytes of the sector with the last correctly written byte to

the FIFO. Whether there is an error or not, an interrupt is

generated at the end of the execution phase, and is cleared

by reading the first result phase byte.

DACK asserted alone, without a RD or WR pulse, is also

counted as a transfer. If pulses of RD or WR are not being

issued for each byte, a DACK pulse must be issued for each

byte so that the Floppy Disk Controller(FDC) can count the

number of bytes correctly.

The VERIFY command, allows easy verification of data

written to the disk without actually transferring the data on

the data bus.

Interrupt Transfer Mode - FIFO Disabled

If interrupt transfer (non-DMA) mode is selected, the appro-

priate IRQ signal is asserted instead of DRQ, when each

byte is ready to be transferred.

The Main Status Register (MSR) should be read to verify

that the interrupt is for a data transfer. The RQM and NON

DMA bits (bits 7 and 5, respectively) in the MSR are set to

1. The interrupt is cleared when the byte is transferred to or

from the Data Register (FIFO). To transfer the data in or out

of the Data register, you must use the address bits of the

FDC together and RD or WR must be active, i.e., A2-0 must

be valid. It is not enough to just assert the address bits of

the FDC. RD or WR must also be active for a read or write

transfer to be recognized.

The microprocessor should transfer the byte within the data

transfer service time (see Section 3.3.7 on page 43). If the

byte is not transferred within the time allotted, an overrun er-

ror is indicated in the result phase when the command ter-

minates at the end of the current sector.

An interrupt is also generated after the last byte is trans-

ferred. This indicates the beginning of the result phase. The

RQM and DIO bits (bits 7 and 6, respectively) in the MSR

are set to 1, and the NON DMA bit (bit 5) is cleared to 0. This

interrupt is cleared by reading the first result byte.

Interrupt Transfer Mode - FIFO Enabled

Interrupt transfer (non-DMA) mode with the FIFO enabled is

very similar to interrupt transfer mode with the FIFO dis-

abled. In this case, the appropriate IRQ signal is asserted

instead of DRQ, under the same FIFO threshold trigger con-

ditions.

The MSR should be read to verify that the interrupt is for a

data transfer. The RQM and non-DMA bits (bits 7 and 5, re-

spectively) in the MSR are set. To transfer the data in or out

of the Data register, you must use the address bits of the

FDC together and RD or WR must be active, i.e., A2-0 must

be valid. It is not enough to just assert the address bits of

the FDC. RD or WR must also be active for a read or write

transfer to be recognized.

Burst mode may be used to hold the IRQ signal active dur-

ing a burst, or burst mode may be disabled to toggle the IRQ

signal for each byte of a burst. The Main Status Register

(MSR) is always valid to the microprocessor. For example,

during a read command, after the last byte of data has been

read from the disk and placed in the FIFO, the MSR still in-

dicates that the execution phase is active, and that data

needs to be read from the Data Register (FIFO). Only after

the last byte of data has been read by the microprocessor

from the FIFO does the result phase begin.

The overrun and underrun error procedures for non-DMA

mode are the same as for DMA mode. Also, whether there

is an error or not, an interrupt is generated at the end of the

execution phase, and is cleared by reading the first result

phase byte.

Software Polling

If non-DMA mode is selected and interrupts are not suitable,

the microprocessor can poll the MSR during the execution

phase to determine when a byte is ready to be transferred.

The RQM bit (bit 7) in the MSR reflects the state of the IRQ

signal. Otherwise, the data transfer is similar to the interrupt

mode described above, whether the FIFO is enabled or dis-

abled.

3.4.3

Result Phase

During the result phase, the microprocessor reads a series

of result bytes from the Data Register (FIFO). These bytes

indicate the status of the command. They may indicate

whether the command executed properly, or may contain

some control information.

See the specific commands in Section 3.7 on page 53 or

Section 3.3.7 on page 43 for details.

These result bytes are read in the order specified for that

particular command. Some commands do not have a result

phase. Also, the number of result bytes varies with each

command. All result bytes must be read from the Data Reg-

ister (FIFO) before the next command can be issued.

As it does for command bytes, the Main Status Register

(MSR) controls the flow of result bytes, and must be polled

by the software before reading each result byte from the

Data Register (FIFO). The RQM bit (bit 7) and DIO bit (bit 6)

of the MSR must both be set before each result byte can be

read.

After the last result byte is read, the Command in Progress

bit (bit 4) of the MSR is cleared, and the controller is ready

for the next command.

For more information, see Section 3.5 on page 48.

3.4.4

Idle Phase

After a hardware or software reset, after the chip has recov-

ered from power-down mode or when there are no com-

mands in progress the controller is in the idle phase. The

controller waits for a command byte to be written to the Data

cleared in the MSR.

After receiving the first command (opcode) byte, the con-

troller enters the command phase. When the command is

completed the controller again enters the idle phase. The

Digital Data Separator (DDS) remains synchronized to the

reference frequency while the controller is idle. While in the

idle phase, the controller periodically enters the drive polling

phase.

PC87309VLJ 数据表(PDF) 47 Page - National Semiconductor (TI)

PC87309VLJ 数据表(HTML) 47 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载