PC87309VLJ datasheet(39/192 Pages) NSC

39 / 192 page

The Floppy Disk Controller (FDC) (Logical Device 0)

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3.3.2

Status Register B (SRB)

Status Register B (SRB) is a read-only diagnostic register

that is valid only in PS/2 drive mode.

SRB can be read at any time while PS/2 drive mode is ac-

tive. In PC-AT drive mode, all bits are in TRI-STATE during

a microprocessor read.

Bit 0 - Motor 0 Status (MTR0)

This bit indicates the complement of the MTR0 output

pin.

This bit is cleared to 0 by a hardware reset and unaffect-

ed by a software reset.

0: MTR0 not active; motor 0 off (default).

1: MTR0 active; motor 0 on.

Bit 1 - Motor 1 Status (MTR1)

This bit indicates the complement of the MTR1 output

pin.

This bit is cleared to 0 by a hardware reset and unaffect-

ed by a software reset.

0: MTR1 not active; motor 1 off (default).

1: MTR1 active.; motor 1 on.

Bit 2 - Write Circuitry Status (WGATE)

This bit indicates the complement of the WGATE output

pin.

0: WGATE not active. The write circuitry of the select-

ed FDD is enabled (default).

1: WGATE active. The write circuitry of the selected

FDD is disabled.

Bit 3 - Read Data Status (RDATA)

If read data was sent, this bit indicates whether an odd

or even number of bits was sent.

Every inactive edge transition of the RDATA disk inter-

face output signal causes this bit to change state.

0: Either no read data was sent or an even number of

bits of read data was sent. (Default)

1: An odd number of bits of read data was sent.

Bit 4 - Write Data Status (WDATA)

If write data was sent, this bit indicates whether an odd

or even number of bits was sent.

Every inactive edge transition of the WDATA disk inter-

face output signal causes this bit to change state.

0: Either no write data was sent or an even number of

bits of write data was sent. (Default)

1: An odd number of bits of write data was sent.

Bit 5 - Drive Select Status

This bit reflects the status of drive select bit 0 in the Dig-

ital Output Register (DOR). See Section 3.3.3.

It is cleared after a hardware reset and unaffected by a

software reset.

0: Either drive 0 or 2 is selected. (Default)

1: Either drive 1 or 3 is selected.

Bits 7,6 - Reserved

These bits are reserved and are always 1.

3.3.3

Digital Output Register (DOR)

DOR is a read/write register that can be written at any time.

It controls the drive select and motor enable disk interface

output signals, enables the DMA logic and contains a soft-

ware reset bit.

The contents of the DOR is set to 00h after a hardware re-

set, and is unaffected by a software reset.

TABLE 3-2 shows how the bits of DOR select a drive and

enable a motor when the FDC is enabled (bit 3 of the Func-

tion Enable Register 1 (FER1) at offset 00h of logical device

8 is 1) and bit 7 of the SuperI/O FDC Configuration register

at index F0h is 1. Bit patterns not shown produce states that

should not be decoded to enable any drive or motor.

When the FDC is enabled and bit 7 of the of the SuperI/O

FDC Configuration register at index F0h is 1, MTR1 pre-

sents a pulse that is the inverse of WR. This pulse is active

whenever an I/O write to address 02h occurs. This pulse is

delayed for between 25 and 80 nsec after the leading edge

of WR. The leading edge of this pulse can be used to clock

data into an external latch (e.g., 74LS175).

TABLE 3-2. Drive and Motor Pin Encoding for Four

Drive Conﬁgurations and Drive Exchange Support

76543210

Reset

Required

SRB Register

Offset 01h

WGATE

WDATA

Drive Select Status

Reserved

MTR0

MTR1

RDATA

PS/2 Drive Mode

Digital Output

Control

Signals

Decoded Functions

MTR DR

765432101010

x x x1x x0 0 - 0 0 0

Activate Drive 0

and Motor 0

x x 1 x x x 0 1-0 0 1

Activate Drive 1

and Motor 1

x1x x x x1 0 - 0 1 0

Activate Drive 2

and Motor 2

1x x x x x1 1 - 0 1 1

Activate Drive 3

and Motor 3

x x x0x x0 0 - 1 0 0

Activate Drive 0 and

Deactivate Motor 0

x x 0 x x x 0 1-1 0 1

Activate Drive 1 and

deactivate Motor 1

x0x x x x1 0 - 1 1 0

Activate Drive 2 and

Deactivate Motor 2

0x x x x x1 1 - 1 1 1

Activate Drive 3 and

Deactivate Motor 3

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