PC87309VLJ datasheet(82/192 Pages) NSC

82 / 192 page

Parallel Port (Logical Device 1)

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Section 4.3.10 "EPP Mode Transfer Operations" on page

85 describes the transfer operations that are possible in

EPP modes.

Bit 0 - Data Strobe Control

Bit 0 directly controls the data strobe signal to the printer

via the STB signal.

This bit is the inverse of the STB signal.

Bit 1 - Automatic Line Feed Control

This bit directly controls the automatic line feed signal to

the printer via the AFD pin. Setting this bit high causes

the printer to automatically feed after each line is printed.

This bit is the inverse of the AFD signal.

0: No automatic line feed (Default)

1: Automatic line feed

Bit 2 - Printer Initialization Control

Bit 2 directly controls the signal to initialize the printer via

the INIT pin. Setting this bit to low initializes the printer.

The value of the INIT signal reflects the value of this bit.

The default setting of 1 on this bit prevents printer initial-

ization in SPP mode, and enables ECP mode after re-

set.

0: Initialize Printer

1: No action (Default)

Bit 3 - Select Input Signal Control

This bit directly controls the select in signal to the printer

via the SLIN signal. Setting this bit high selects the print-

er.

It is the inverse of the SLIN signal.

This bit must be cleared to 0 before enabling the EPP or

ECP mode.

0: Printer not selected. (Default)

1: Printer selected and online.

Bit 4 - Interrupt Enable

Bit 4 controls the interrupt generated by the ACK signal.

Its function changes slightly depending on the parallel

port mode selected.

In ECP mode, this bit should be set to 0.

In the following description, IRQx indicates an interrupt

allocated for the parallel port.

0: In SPP Compatible, SPP Extended and EPP

modes, IRQx is ﬂoated. (Default)

1: In SPP Compatible mode, IRQx follows ACK transi-

tions.

In SPP Extended mode, IRQx is set active on the trail-

ing edge of ACK.

In EPP modes, IRQx follows ACK transitions, or is

set when an EPP time-out occurs.

Bit 5 - Direction Control

This bit determines the direction of the parallel port in

SPP Extended mode only. In the (default) SPP Compat-

ible mode, this bit has no effect, since the port functions

for output only.

This is a read/write bit in EPP modes. In SPP modes it

is a write only bit. A read from it returns 1.

In SPP Compatible mode and in EPP modes it does not

control the direction. See TABLE 4-4 "SPP DTR Regis-

ter Read and Write Modes" on page 80.

0: Data output to PD7-0 in SPP Extended mode dur-

ing write cycles. (Default)

1: Data input from PD7-0 in SPP Extended mode dur-

ing read cycles.

Bits 7,6 - Reserved

These bits are reserved and are always 1.

4.3

ENHANCED PARALLEL PORT (EPP) MODES

EPP modes allow greater throughput than SPP modes by

supporting faster transfer times (8, 16 or 32-bit data trans-

fers in a single read or write operation) and a mechanism

that allows the system to address peripheral device regis-

ters directly. Faster transfers are achieved by automatically

generating the address and data strobes.

The connector pin assignments for these modes are listed

in TABLE 4-12 "Parallel Port Pin Out" on page 101.

EPP modes support revision 1.7 and revision 1.9 of the

IEEE 1284 standard, as shown in TABLE 4-1 "Parallel Port

Mode Selection" on page 80.

In Legacy mode, EPP modes are supported for a parallel

port whose base address is 278h or 378h, but not for a par-

allel port whose base address is 3BCh. (There are no EPP

registers at 3BFh.) In both Legacy and Plug and Play

modes, bits 2, 1 and 0 of the parallel port base address

must be 000 in EPP modes.

SPP-type data transactions may be conducted in EPP

modes. The appropriate registers are available for this

type of transaction. (See TABLE 4-5 "Enhanced Parallel

Port (EPP) Registers".) As in the SPP modes, software

must generate the control signals required to send or re-

ceive data.

4.3.1

EPP Register Set

TABLE 4-5 lists the EPP registers. All are single-byte regis-

ters.

Bits 0, 1 and 3 of the CTR register must be 0 before the EPP

registers can be accessed, since the signals controlled by

these bits are controlled by hardware during EPP accesses.

Once these bits are set to 0 by the software driver, multiple

EPP access cycles may be invoked.

When EPP modes are enabled, the software can perform

SPP Extended mode cycles. In other words, if there is no

access to one of the EPP registers, EPP Address (ADDR)

76543210

Reset

Required

SPP Control Register

(CTR)

Offset 02h

Printer Initialization Control

Interrupt Enable

Direction Control

Reserved

Data Strobe Control

Parallel Port Input Control

Automatic Line Feed Control

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