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PC87309VLJ 数据表(PDF) 25 Page - National Semiconductor (TI) |
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PC87309VLJ 数据表(HTML) 25 Page - National Semiconductor (TI) |
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25 / 192 page  Configuration 25 www.national.com 2.3.2 Configuration Register Summary The tables in this section specify the Index, type (read/write), reset values and configuration register or action that controls each register associated with each function. When the reset value is not fixed, the table indicates what controls the value or points to another section that provides this information. Soft reset is related to a reset executed by utilizing the reset bit (bit 0) of the Configuration Control Register. (See TABLE 2-4 "Plug and Play (PnP) Standard Control Registers" on page 22. Access to the KBC Configuration Registers for Logical De- vice 6 (see TABLE 2-17 "KBC Configuration Registers for Keyboard - Logical Device 6" on page 28) is controlled by bit 4 of the SIOCF1 Register. Setting this bit to 1 locks the KBC Configuration Registers and disables access to Logi- cal Device 6. All writes are ignored and all reads return 0 when you attempt to access the locked registers. However, locking the KBC configuration registers does not affect ac- cess to the KBC Command Data and Status Registers. TABLE 2-10. Card Control Registers TABLE 2-11. FDC Configuration Registers - Logical Device 0 Index Type Hard Reset Soft Reset Configuration Register or Action 00h W 00h PnP ISA Set RD_DATA Port. 01h R Serial Isolation. 02h W PnP ISA PnP ISA Configuration Control. 03h W 00h PnP ISA Wake[CSN]. 04h R Resource Data. 05h R Status. 06h R/W 00h PnP ISA Card Select Number (CSN). 07h R/W 00h PnP ISA Logical Device Number. 20h R E0h E0h Read only SID Register. Bits 2-0 - Revision ID Bit 7-3 - Chip ID 21h R/W See Section 2.4.2. No Effect SuperI/O Configuration 1 Register (SIOCF1). 22h R/W See Section 2.4.3. No Effect SuperI/O Configuration 2 Register (SIOCF2). 27h R xx xx SRID Register. Bits 7-0 - Revision ID 2Eh xx xx Reserved for National Semiconductor use only. Index R/W Hard Reset Soft Reset Configuration Register or Action 30h R/W 00h or 01h See CFG0 in Section 2.1.1. 00h or 01h See CFG0 in Section 2.1.1. Activate. See also FER1 of the Power Management device (Logical Device 4). 31h R/W 00h 00h I/O Range Check. 60h R/W 03h 03h Base Address MSB Register. Bits 7-3 (for A15-11) are read only, 00000b. 61h R/W F2h F2h Base Address LSB Register. Bits 2 and 0 (for A2 and A0) are read only, 0,0. 70h R/W 06h 06h Interrupt Select. 71h R/W 03h 03h Interrupt Type. Bit 1 is read/write; other bits are read only. 74h R/W 02h 02h DMA Channel Select. 75h R 04h 04h Report no DMA assignment. F0h R/W See Section 2.5.1. No Effect SuperI/O FDC Configuration Register. F1h R/W See Section 2.5.2. No Effect Drive ID Register. |
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