PC87309VLJ datasheet(21/192 Pages) NSC

21 / 192 page

Configuration

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TABLE 2-3. Parallel Port Address Range Allocation

a. The SuperI/O processor does not decode the Parallel Port outside this range.

A15-11 are read only 0 in all base address registers. To en-

sure full 16-bit decoding as required by PC95/PC97, you

must externally decode A15-11 (in Two-UART mode) or

A15-12 (in Full-IR mode), and drive them via AEN as shown

below:

In Two-UART mode (A11 not available)

AEN<=(AEN|A11|A12|A13|A14|A15)

where | = logical OR

In Full-IR mode (A11 available on pin 93)

AEN<=(AEN|A12|A13|A14|A15)

where | = logical OR

2.3

THE CONFIGURATION REGISTERS

The configuration registers control the setup of the

PC87309VLJ. Their major functions are to:

Identify the chip

Enable major functions (such as, the Keyboard Control-

ler (KBC) for the keyboard and the mouse, the Floppy

Disc Controller (FDC), UARTs, parallel and general pur-

pose ports, power management and pin functionality)

Define the I/O addresses of these functions

Define the status of these functions upon reset

Section 2.3.2 "Configuration Register Summary" on page

25 summarizes information for each register of each func-

tion. In addition, the following non-standard, or card control,

registers are described in detail, in Section 2.4 "CARD

CONTROL REGISTERS" on page 28.

Card Control Registers

— SID Register

— SuperI/O Conﬁguration 1 Register (SIOCF1)

— SuperI/O Conﬁguration 2 Register (SIOCF2)

— SRID Register

— NSC-Test Register

FDC Configuration Registers (Logical Device 0)

— SuperI/O FDC Conﬁguration Register

— Drive ID Register

SuperI/O Parallel Port Conﬁguration Register (Logical

Device 1)

SuperI/O UART2 and Infrared Conﬁguration Register

(Logical Device 2)

SuperI/O UART1 Conﬁguration Register (Logical De-

vice 3)

SuperI/O KBC Configuration Register (Logical Device 6)

2.3.1

Standard Plug and Play (PnP) Register Definitions

TABLES 2-4 through 2-9 describe the standard PnP regis-

ters. For more detailed information on these registers,

refer the

“Plug and Play ISA Specification, Version 1.0a,

May 5, 1994”

Parallel Port Mode

SuperI/O Parallel Port

Conﬁguration Register Bits

Decoded Range a

SPP

Three registers, from base (address) to base + 02h

EPP (Non IEEE1284 Mode 4)

Eight registers, from base to base + 07h

IEEE1284, No Mode 4,

No Internal Conﬁguration

Six registers, from base to base + 02h and from

base + 400h to base + 402h

IEEE1284 with Mode 4,

No Internal Conﬁguration

11 registers, from base to base + 07h and from

base + 400h to base + 402h

IEEE1284 with Mode 4,

Conﬁguration within Parallel Port

16 registers, from base to base + 07h and from

base + 400h to base + 407h

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