PC87309VLJ datasheet(20/192 Pages) NSC

20 / 192 page

Configuration

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TABLE 2-1. Strap Pins and Base Addresses

2.2

SOFTWARE CONFIGURATION

2.2.1

Accessing the Configuration Registers

Only two system I/O addresses are required to access any

of the configuration registers. The Index and Data register

pair is used to access registers for all read and write opera-

tions.

In a write operation, the target configuration register is iden-

tified, based on a value that is loaded into the Index register.

Then, the data to be written into the configuration register is

transferred via the Data register.

Similarly, for a read operation, first the source configuration

Index register. Then, the data to be read is transferred via

the Data register.

Reading the Index register returns the last value loaded into

the Index register. Reading the Data register returns the

data in the configuration register pointed to by the Index

If, during reset, the Base Address 1 (BADDR1) signal is low

(0), the Index and Data registers are not accessible imme-

diately after reset. As a result, all configuration registers of

the PC87309VLJ are also not accessible at this time. To ac-

cess these registers, you must apply the PnP ISA protocol.

If during reset, the Base Address 1 (BADDR1) signal is high

(1), all configuration registers are accessible immediately

after reset.

It is up to the configuration software to guarantee no con-

flicts between the registers of the active (enabled) logical

devices, between IRQ signals and between DMA channels.

If conflicts of this type occur, the results are unpredictable.

To maintain compatibility with other SuperI/O‘s, the value of

reserved bits may not be altered. Use read-modify-write.

2.2.2

Address Decoding

The address decoding of all logical devices, as well as the

configuration registers, consists of 11 non-zero address bits

(A10-0) and AEN. The supported I/O range is 0 to 3FFh.

The only non-zero A11 address decoding is the PnP

WRITEA_DATA port at ISA address A79h, when working in

full PnP mode.

In full PnP mode, the addresses of the Index and Data reg-

isters that access the Configuration Registers are decoded

using pins A10-0, according to the ISA PnP specification.

In PnP Motherboard mode, the addresses of the Index and

Data registers that access the Configuration Registers are

decoded using pins A10-1. Pin A0 distinguishes between

these two registers.

KBC and mouse register addresses are decoded using pins

A1,0 and A10-3. Pin A2 distinguishes between the device

registers.

Power Management (PM) register addresses are decoded

using pins A10-1.

FDC and UART register addresses are decoded using pins

A10-3.

Parallel Port (PP) modes determine which pins are used for

are used to decode base address and which address pins

are used to distinguish between registers in each mode.

TABLE 2-2. Address Pins Used for Parallel Port

NOTE: When working with the Parallel Port in ECP mode

and enabling the registers at base (address)+403h,

base+404h, base+405h (the default state) both the

Parallel Port base address and the ECP registers

are 8 byte aligned and take 8 bytes of the I/O

space.

CFG0

BADDR1

BADDR0

Address

Conﬁguration Type

Index Register

Data Register

0279h

Write Only

Write: 0A79h

Read: RD_DATA Port

Full PnP ISA mode

Full-IR mode

015Ch Read/Write

015Dh Read/Write

PnP Motherboard mode

Full-IR mode

002Eh Read/Write

002Fh Read/Write

PnP Motherboard mode

Full-IR mode

015Ch Read/Write

015Dh Read/Write

PnP Motherboard mode

Two-UART mode

002Eh Read/Write

002Fh Read/Write

PnP Motherboard mode

Two-UART mode

PP Mode

Pins Used to

Decode Base

Address

Pins Used to

Distinguish between

Registers

SPP

A10-2

A1,0

ECP

A9-2

A1,0 and A10

EPP

A10-3

A2-0

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