PC87309VLJ datasheet(4/192 Pages) NSC

4 / 192 page

Table of Contents

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Table of Contents

Highlights....................................................................................................................................................... 1

1.0

Signal/Pin Connection and Description

1.1

CONNECTION DIAGRAM ......................................................................................................... 12

1.2

SIGNAL/PIN DESCRIPTIONS ................................................................................................... 13

2.0

Configuration

2.1

HARDWARE CONFIGURATION ............................................................................................... 19

2.1.1

Wake Up Options ........................................................................................................ 19

2.1.2

The Index and Data Register Pair ............................................................................... 19

2.2

SOFTWARE CONFIGURATION ............................................................................................... 20

2.2.1

Accessing the Configuration Registers ........................................................................ 20

2.2.2

Address Decoding ....................................................................................................... 20

2.3

THE CONFIGURATION REGISTERS ....................................................................................... 21

2.3.1

Standard Plug and Play (PnP) Register Definitions .................................................... 21

2.3.2

Configuration Register Summary ................................................................................ 25

2.4

CARD CONTROL REGISTERS ................................................................................................ 28

2.4.1

SID Register ................................................................................................................ 28

2.4.2

SuperI/O Configuration 1 Register (SIOCF1) .............................................................. 28

2.4.3

SuperI/O Configuration 2 Register (SIOCF2) .............................................................. 29

2.4.4

SRID Register .............................................................................................................. 29

2.5

FDC CONFIGURATION REGISTERS (LOGICAL DEVICE 0) .................................................. 30

2.5.1

SuperI/O FDC Configuration Register ......................................................................... 30

2.5.2

Drive ID Register ......................................................................................................... 30

2.6

SUPERI/O PARALLEL PORT CONFIGURATION REGISTER (LOGICAL DEVICE 1) ............. 30

2.7

SUPERI/O UART2 AND INFRARED CONFIGURATION REGISTER (LOGICAL DEVICE 2) .. 31

2.8

SUPERI/O UART1 CONFIGURATION REGISTER (LOGICAL DEVICE 3) .............................. 32

2.9

SUPERI/O KBC CONFIGURATION REGISTER (LOGICAL DEVICE 6) .................................. 32

2.10

CONFIGURATION REGISTER BITMAPS ................................................................................ 32

3.0

The Floppy Disk Controller (FDC) (Logical Device 0)

3.1

FDC FUNCTIONS ..................................................................................................................... 34

3.1.1

Microprocessor Interface ............................................................................................. 34

3.1.2

System Operation Modes ............................................................................................ 34

3.2

DATA TRANSFER ..................................................................................................................... 35

3.2.1

Data Rates ................................................................................................................... 35

3.2.2

The Data Separator ..................................................................................................... 35

3.2.3

Perpendicular Recording Mode Support ..................................................................... 36

3.2.4

Data Rate Selection ..................................................................................................... 36

3.2.5

Write Precompensation ............................................................................................... 37

3.2.6

FDC Low-Power Mode Logic ....................................................................................... 37

3.2.7

Reset ........................................................................................................................... 37

3.3

THE REGISTERS OF THE FDC ............................................................................................... 37

PC87309VLJ 数据表(PDF) 4 Page - National Semiconductor (TI)

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