PC87309VLJ datasheet(16/192 Pages) NSC

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Signal/Pin Connection and Description

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IRSL0

IRSL1

IRSL2

100

UART2

Output

Group 12

Infrared Control Signals 0, 1 and 2 – These signals control the

Infrared analog front end. The pins on which these signals are driven

is determined by the SuperI/O Conﬁguration 2 register (index 22h).

SeeTABLE 1-2 for more information.

IRSL0 is multiplexed on pin 100 with SOUT2, IRRX2 and ID0, and is

available only in Full-IR mode.

IRSL1 is multiplexed on pin 98 with RTS2 and ID1, and is available

only in Full-IR mode.

IRSL2 is multiplexed on pin 96 with DTR2, BOUT2 and ID2, and is

available only in Full-IR mode.

IRTX

UART2

Output

Group 12

Infrared Transmit – Infrared serial output data.

This signal is multiplexed with DENSEL only in Two-UART mode.

KBCLK

KBC

I/O

Group 6

Keyboard Clock – This I/O pin transfers the keyboard clock between

the SuperI/O chip and the external keyboard using the PS/2 protocol.

This pin is connected internally to the internal TO signal of the KBC.

KBDAT

KBC

I/O

Group 6

Keyboard Data – This I/O pin transfers the keyboard data between

the SuperI/O chip and the external keyboard using the PS/2 protocol.

This pin is connected internally to KBC’s P10.

MCLK

KBC

I/O

Group 6

Mouse Clock – This I/O pin transfers the mouse clock between the

SuperI/O chip and the external keyboard using the PS/2 protocol.

This pin is connected internally to KBC’s T1.

MDAT

KBC

I/O

Group 6

Mouse Data – This I/O pin transfers the mouse data between the

SuperI/O chip and the external keyboard using the PS/2 protocol.

This pin is connected internally to KBC’s P11.

ISA-Bus

Input

Group 1

Master Reset – An active high MR input signal resets the controller

to the idle state, and resets all disk interface output signals to their

inactive states. MR also clears the DOR, DSR and CCR registers,

and resets the MODE command, CONFIGURE command, and LOCK

command parameters to their default values. MR does not affect the

SPECIFY command parameters. MR sets the conﬁguration registers

to their selected default values.

MTR1,0

46,45

FDC

Output

Group 11

Motor Select 1,0 – These motor enable lines for drives 0 and 1 are

controlled by bits D7-4 of the Digital Output Register (DOR). They are

output signals that are active when they are low. They are encoded with

information to control four FDDs when bit 7 of the SuperI/O FDC

Conﬁguration register is set See TABLE 1-2 for more information. See

DR1,0.

MTR0 is multiplexed with DRATE0 only in Two-UART mode.

MTR1 is multiplexed with P12 only in Two-UART mode.

P12

94, 46 or

KBC

I/O

Group 7

I/O Port – KBC quasi-bidirectional port for general purpose input and

output.

P12 is multiplexed on pin 43 with IRRX1 and DRATE0, on pin 46 with

MTR1, and on pin 94 with DCD2.

P21,P20

64,63

KBC

I/O

Group 7

I/O Port – KBC open-drain signals for general purpose input and

output. These signals are controlled by KBC ﬁrmware.

PD7-0

82-75

Parallel Port

I/O

Group 9

Parallel Port Data – These bidirectional signals transfer data to and

from the peripheral data bus and the appropriate parallel port data

Section 10.1.

Parallel Port

Input

Group 2

Group 3

Paper End – This input signal is set high by the printer when it is out

of paper. This pin has an internal weak pull-up or pull-down resistor.

RDATA

FDC

Input

Group 1

Read Data – This input signal holds raw serial data read from the

Floppy Disk Drive (FDD).

Signal/Pin

Name

Number

Module

I/O and

Group #

Function

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