PC87309VLJ datasheet(31/192 Pages) NSC

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Configuration

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Bit 1 - Clock Enable

0: Parallel port clock disabled.

ECP modes and EPP timeout are not functional

when the logical device is active. Registers are

maintained.

1: Parallel port clock enabled.

All operation modes are functional when the logical

device is active. This bit is ANDed with a bit of the

PMC3 register of the Power Management device

(Logical Device4).

Bit 2,3 - Reserved

Bit 4 - Conﬁguration Bits within the Parallel Port

0: The registers at base (address) + 403h, base +

404h and base + 405h are not accessible (reads

and writes are ignored).

1: When IEEE1284 mode is selected by bits 7

through 5, the registers at base (address) + 403h,

base + 404h and base + 405h are accessible.

This option supports run-time conﬁguration within

the Parallel Port address space. An 8-byte (and

1024-byte) aligned base address is required to ac-

cess these registers. See Chapter 4 "Parallel Port

(Logical Device 1)" on page 79 for details.

Bit 7-5 - Parallel Port Mode Select

Bit 5 is the LSB.

Selection of EPP 1.7 or 1.9 in ECP mode 4 is controlled

by bit 4 of the Control2 configuration register of the par-

allel port at offset 02h. See Section 4.5.17 "Control2

000: SPP Compatible mode. PD7-0 are always output

signals.

001: SPP Extended mode. PD7-0 direction controlled

by software.

010:EPP 1.7 mode.

011:EPP 1.9 mode.

100:IEEE1284 mode (selects IEEE1284 register set),

with no support for EPP mode.

101:Reserved.

110:Reserved.

111:IEEE1284 mode (selects IEEE1284 register set),

with EPP mode selectable as mode 4.

2.7

SUPERI/O UART2 AND INFRARED

CONFIGURATION REGISTER (LOGICAL DEVICE 2)

This read/write register is reset by hardware to 02h.

Bit 0 - TRI-STATE Control for UART2 signals

This bit controls the TRI-STATE status of UART signals

(except IRQ and DMA signals) when UART2 is inactive

(disabled). This bit is ORed with a bit of the PMC1 reg-

ister of the Power Management device (Logical

Device4).

0: Signals not in TRI-STATE.

1: Signals in TRI-STATE.

Bit 1 - Power Mode Control

0: Low power mode.

UART2 Clock disabled. UART2 output signals are

set to their default state. The RI input signal can be

programmed to generate an interrupt. Registers

are maintained.

1: Normal power mode.

UART2 clock enabled. The UART2 is functional

when the logical device is active. This bit is ANDed

with a bit of the PMC3 register of the Power Man-

agement device (Logical Device 4).

Bit 2 - Busy Indicator

This read-only bit can be used by power management

software to decide when to power down UART2 logical

device. This bit is also accessed via the PMC3 register

of the Power Management device (Logical Device 4).

0: No transfer in progress.

1: Transfer in progress.

Bits 6-3 - Reserved

Bit 7 - Bank Select Enable

Enables bank switching for UART2. If this bit is cleared,

all attempts to access the extended registers are ig-

nored.

TRI-STATE Control for

Bank Select Enable

76543210

Reset

Required

Index F0h

Configuration Register,

SuperI/O UART2

Power Mode Control

Busy Indicator

Reserved

UART2 Pins

PC87309VLJ 数据表(PDF) 31 Page - National Semiconductor (TI)

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