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PC87309VLJ 数据表(PDF) 83 Page - National Semiconductor (TI) |
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PC87309VLJ 数据表(HTML) 83 Page - National Semiconductor (TI) |
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83 / 192 page  Parallel Port (Logical Device 1) 83 www.national.com or EPP Data Registers 0-3 (DATA0-3), EPP modes behave like SPP Extended mode, except for the interrupt, which is pulse triggered instead of level triggered. Bit 7 of STR (BUSY status) must be set to 1 before writing to DTR in EPP modes to ensure data output to PD7-0. The enhanced parallel port monitors the IOCHRDY signal during EPP cycles. If IOCHRDY is driven low for more then 10 µsec, an EPP time-out event occurs, which aborts the cycle by asserting IOCHRDY, thus releasing the system from a stuck EPP peripheral device. (This time-out event is only functional when the clock is applied to this logical de- vice). When the cycle is aborted, ASTRB or DSTRB becomes in- active, and the time-out event is signaled by asserting bit 0 of STR. If bit 4 of CTR is 1, the time-out event also pulses the IRQ5 or IRQ7 signals when enabled. (IRQ5 and IRQ7 can be routed to any other IRQ lines via the Plug and Play block). EPP cycles to the external device are activated by invoking read or write cycles to the EPP. TABLE 4-5. Enhanced Parallel Port (EPP) Registers 4.3.2 SPP or EPP Data Register (DTR) The DTR register is the SPP Compatible or SPP Extended data register. A write to DTR sets the state of the eight data pins on the 25-pin D-shell connector. 4.3.3 SPP or EPP Status Register (STR) This status port is read only. A read presents the current status of the five pins on the 25-pin D-shell connector, and the IRQ. The bits of this register have the identical function in EPP mode as in SPP mode. See Section 4.2.3 "Status Register (STR)" on page 81 for a detailed description of each bit. 4.3.4 SPP or EPP Control Register (CTR) This control port is read or write. A write operation to it sets the state of four pins on the 25-pin D-shell connector, and controls both the parallel port interrupt enable and direction. The bits of this register have the identical function in EPP modes as in SPP modes. See Section 4.2.4 "SPP Control Register (CTR)" on page 81 for a detailed description of each bit. 4.3.5 EPP Address Register (ADDR) This port is added in EPP modes to enhance system throughput by enabling registers in the remote device to be directly addressed by hardware. This port can be read or written. Writing to it initiates an EPP device or register selection operation. Offset Name Description Mode R/W 00h DTR SPP Data SPP or EPP R/W 01h STR SPP Status SPP or EPP R 02h CTR SPP Control SPP or EPP R/W 03h ADDR EPP Address EPP R/W 04h DATA0 EPP Data Port 0 EPP R/W 05h DATA1 EPP Data Port 1 EPP R/W 06h DATA2 EPP Data Port 2 EPP R/W 07h DATA3 EPP Data Port 3 EPP R/W 76543210 Reset Required 0 0 0 0 0 0 0 0 SPP or EPP Data Register (DTR) Offset 00h D2 D4 D5 D6 D7 D0 D1 D3 Data Bits 76543210 Reset Required 1 1 1 1 1 1 1 1 SPP or EPP Status Register (STR) Offset 01h IRQ Status SLCT Status PE Status Time-Out Status Reserved ERR Status ACK Status Printer Status 76543210 Reset Required 0 0 0 0 0 0 1 1 SPP or EPP Control Register (CTR) Offset 02h Printer Initialization Control Interrupt Enable Direction Control Reserved Reserved Data Strobe Control Automatic Line Feed Control Parallel Port Input Control |
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