PC87309VLJ datasheet(96/192 Pages) NSC

96 / 192 page

Parallel Port (Logical Device 1)

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TABLE 4-11. ECP Modes

FIGURE 4-5. ECP Forward Write Cycle

Backward Direction (Bit 5 of DCR is 1)

When the ECP is in the backward direction, and the FIFO is

not full (bit 1 of ECR is 0), the ECP issues a read cycle to

the peripheral device and monitors the BUSY signal. If

BUSY is high the byte is a data byte and it is pushed into the

FIFO. If BUSY is low the byte is a command byte.

The ECP checks bit 7 of the command byte. If it is high the

byte is ignored, if it is low the byte is tagged as an RLC byte

(not pushed into the FIFO but used as a Run Length Count

to expand the next byte read). Following an RLC read the

ECP issues a read cycle from the peripheral device to read

the data byte to be expanded. This byte is considered a

data byte, regardless of its BUSY state (even if it is low).

This byte is pushed into the FIFO (RLC+1) times (e.g. for

RLC=0, push the byte once. For RLC=127 push the byte

128 times).

When the ECP is in the backward direction, and the FIFO is

not empty (bit 0 of ECR is 0), the FIFO can be emptied by

software reads from the FIFO register (true only for the

TFIFO in mode 011, not for AFIFO or CFIFO reads).

When DMA is enabled (bit 3 of ECR is 1 and bit 2 of ECR is

0) the ECP automatically issues DMA requests to empty the

FIFO (only in mode 011).

ECP (Backward) Read Cycle

An ECP read cycle starts when the ECP drives AFD low.

The peripheral device drives BUSY high for a normal data

read cycle, or drives BUSY low for a command read cycle,

and drives the byte to be read onto PD7-0.

When ACK is asserted the ECP drives AFD high. When

AFD is high the peripheral device deasserts ACK. The ECP

reads the PD7-0 byte, then drives AFD low. When AFD is

low the peripheral device may change BUSY and PD7-0

states in preparation for the next cycle

ECP Mode

(ECR Bits)

ECP Mode

Name

Operation Description

765

Standard

Write cycles are under software control.

STB, AFD, INIT and SLIN are open-drain output signals.

Bit 5 of DCR is forced to 0 (forward direction) and PD7-0 are driven.

The FIFO is reset (empty).

Reading DATAR returns the last value written to DATAR.

PS/2

Read and write cycles are under software control.

The FIFO is reset (empty).

STB, AFD, INIT and SLIN are push-pull output signals.

Parallel Port

FIFO

Write cycles are automatic, i.e., under hardware control (STB is controlled by hardware).

Bit 5 of DCR is forced to 0 internally (forward direction) and PD7-0 are driven.

STB, AFD, INIT and SLIN are push-pull output signals.

ECP FIFO

The FIFO direction is automatic, i.e., controlled by bit 5 of DCR.

Read and write cycles to the device are controlled by hardware (STB and AFD are

controlled by hardware).

STB, AFD, INIT and SLIN are push-pull output signals.

EPP

EPP mode is enabled by bits 7 through 5 of the SuperI/O Parallel Port Conﬁguration

In this mode, registers DATAR, DSR, and DCR are used as registers at offsets 00h, 01h and

02h of the EPP instead of registers DTR, STR, and CTR.

STB, AFD, INIT, and SLIN are push-pull output buffers.

When there is no access to one of the EPP registers (ADDR, DATA0, DATA1, DATA2 or

DATA3), mode 100 behaves like mode 001, i.e., software can perform read and write cycles.

The software should check that bit 7 of the DSR is 1 before reading or writing the DATAR

Reserved

FIFO Test

The FIFO is accessible via the TFIFO register.

The ECP does not issue ECP cycles to ﬁll or empty the FIFO.

Conﬁguration CNFGA and CNFGB registers are accessible.

BUSY

STB

PD7-0

AFD

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