PC87309VLJ datasheet(74/192 Pages) NSC

74 / 192 page

The Floppy Disk Controller (FDC) (Logical Device 0)

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TABLE 3-23. Constant Multipliers for Delay After Processing Factor and Delay Ranges

TABLE 3-24. Constant Multipliers for Delay Before Processing Factor and Delay Ranges

TABLE 3-25. STEP Time Interval Calculation

Third Command Phase Byte

Bit 0 - DMA

This bit selects the data transfer mode in the execution

phase of a read, write, or scan operation.

Data can be transferred between the microprocessor

and the controller during execution in DMA mode or in

non-DMA mode, i.e., interrupt transfer mode or software

polling mode.

See Section 3.4.2 on page 45 for a description of these

modes.

0: DMA mode is selected.

1: Non-DMA mode is selected.

Bits 3-0 - Delay Before Processing Factor

These bits specify a factor that is multiplied by a con-

stant to determine the delay before command process-

ing starts, i.e., from selection of a drive motor until a

read or write operation starts.

The value of the Motor Timer Values (TMR) bit (bit 7) of

the second command phase byte in the MODE com-

mand determines which group of constants and delay

ranges to use. See “Bit 7 - Motor Timer Values (TMR)”

on page 60.

The specific constant that will be multiplied by this factor

to determine the actual delay before processing for

each data transfer rate is shown in TABLE 3-24 on page

74.

Use the smallest possible value for this factor, except 0,

i.e., 1. If this factor is 0, the value128 is used.

Execution Phase

Internal registers are written.

Result Phase

None.

3.7.22

The VERIFY Command

The VERIFY command verifies the contents of data and/or

address fields after they have been formatted or written.

VERIFY reads logical sectors containing a normal data Ad-

dress Mark (AM) from the selected drive, without transfer-

ring the data to the host.

The TC signal cannot terminate this command since no

data is transferred. Instead, VERIFY simulates a TC signal

by setting the Enable Count (EC) bit to1. In this case, VER-

IFY terminates when the number of sectors read equals the

number of sectors to read, i.e., Sectors to read Count (SC).

If SC = 0 then 256 sectors will be verified.

When EC is 0, VERIFY ends when the End of the Track

(EOT) sector number equals the number of the sector

checked. In this case, the ninth command phase byte is not

needed and should be set to FFh.

TABLE 3-26 on page 75 shows how different values for the

VERIFY parameters affect termination.

Command Phase

Data Transfer

Rate (bps)

Bit 7 of MODE (TMR) = 0

Bit 7 of MODE (TMR) = 1

Constant Multiplier

Permitted Range (msec)

Constant Multiplier

Permitted Range (msec)

1 M

8 -128

512

512 - 8192

500 K

16 - 256

512

512 - 8192

300 K

80 / 3

26.7 - 427

2560 / 3

853 - 13653

250 K

32 - 512

1024

1024 -16384

Data Transfer

Rate (bps)

Bit 7 of MODE (TMR) = 0

Bit 7 of MODE (TMR) = 1

Constant Multiplier

Permitted Range (msec)

Constant Multiplier

Permitted Range (msec)

1 M

1 -128

32 - 4096

500 K

1 -128

32 - 4096

300 K

10 / 3

3.3 - 427

160 / 3

53 - 6827

250 K

4 - 512

64 - 8192

Data Transfer

Rate (bps)

Calculation of Time

Interval

Permitted

Range (msec)

1 M

(16

− SRT) / 2

0.5 - 8

500 K

(16

− SRT)

1 - 16

300 K

(16

− SRT) x 1.67

1.67 - 26.7

250 K

(16

− SRT) x 2

2 - 32

76543210

MFM

10110

XXXX

DS1

DS0

Track Number

Head Number

Sector Number

Bytes-Per-Sector Code

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