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PC87309VLJ 数据表(PDF) 40 Page - National Semiconductor (TI) |
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PC87309VLJ 数据表(HTML) 40 Page - National Semiconductor (TI) |
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40 / 192 page  The Floppy Disk Controller (FDC) (Logical Device 0) 40 www.national.com Usually, the motor enable and drive select output signals for a particular drive are enabled together. TABLE 3-3 shows the DOR hexadecimal values that enable each of the four drives. TABLE 3-3. Drive Enable Hexadecimal Values The motor enable and drive select signals for drives 2 and 3 are only available when four drives are supported, i.e., bit 7 of the SuperI/O FDC Configuration register at index F0h is 1, or when drives 2 and 0 are exchanged. These signals require external logic. Bits 1,0 - Drive Select These bits select a drive, so that only one drive select output signal is active at a time. See “Bit 7 - Four Drive Control” on page 30 and “Bits 3,2 - Logical Drive Control (Enhanced TDR Mode Only)” on page 41 for more information. 00: Drive 0 is selected. (Default) 01: Drive 1 is selected. 10: If four drives are supported, or drives 2 and 0 are exchanged, drive 2 is selected. 11: If four drives are supported, drive 3 is selected. Bit 2 - Reset Controller This bit can cause a software reset. The controller re- mains in a reset state until this bit is set to 1. A software reset affects the CONFIGURE and MODE commands. See Sections 3.7.2 on page 55 and 3.7.7 on page 60, respectively. A software reset does not affect the Data rate Select Register (DSR), Configuration Con- trol Register (CCR) and other bits of this register (DOR). This bit must be low for at least 100 nsec. There is enough time during consecutive writes to the DOR to re- set software by toggling this bit. 0: Reset controller. (Default) 1: No reset. Bit 3 - DMA Enable (DMAEN) In PC-AT drive mode, this bit enables DMA operations by controlling DACK, TC and the appropriate DRQ and IRQ DMA signals. In PC-AT mode, this bit is set to 0 af- ter reset. In PS/2 drive mode, this bit is reserved, and DACK, TC and the appropriate DRQ and IRQ signals are enabled. During reset, these signals remain enabled. 0: In PC-AT drive mode, DMA operations are dis- abled. DACK and TC are disabled, and the appro- priate DRQ and IRQ signals are put in TRI-STATE. (Default) 1: In PC-AT drive mode, DMA operations are enabled, i.e., DACK, TC and the appropriate DRQ and IRQ signals are all enabled. Bit 4- Motor Enable 0 If four drives are supported (bit 7 of the SuperI/O FDC Configuration register at index F0h is 1), this bit may control the motor output signal for drive 0, depending on the remaining bits of this register. See TABLE 3-2 on page 39. If two drives are supported (bit 7 of the SuperI/O FDC Configuration register at index F0h is 0), this bit controls the motor output signal for drive 0. 0: The motor signal for drive 0 is not active. 1: The motor signal for drive 0 is active. Bit 5 - Motor Enable 1 If four drives are supported (bit 7 of the SuperI/O FDC Configuration register at index F0h is 1), this bit may control the motor output signal for drive 0, depending on the remaining bits of this register. See TABLE 3-2. If two drives are supported (bit 7 of the SuperI/O FDC Configuration register at index F0h is 0), this bit controls the motor output signal for drive 1. 0: The motor signal for drive 1 is not active. 1: The motor signal for drive 1 is active. Bit 6 - Motor Enable 2 If drives 2 and 0 are exchanged (see "Bits 3,2 - Logical Drive Control (Enhanced TDR Mode Only)" on page 41), or if four drives are supported (bit 7 of the SuperI/O FDC Configuration register at index F0h is 1), this bit controls the motor output signal for drive 2. See TABLE 3-2. 0: The motor signal for drive 2 is not active. 1: The motor signal for drive 2 is active. Bit 7 - Motor Enable 3 If four drives are supported (bit 7 of the SuperI/O FDC Configuration register at index F0h is 1), this bit may control the motor output signal for drive 3, depending on the remaining bits of this register. See TABLE 3-2. 0: The motor signal for drive 3 is not active. 1: The motor signal for drive 3 is active. Drive DOR Value (Hex) 01C 12D 24E 38F 76543210 Reset Required 0 0 0 0 0 0 0 0 Digital Output Register (DOR) Offset 02h Reset Controller Motor Enable 0 Motor Enable 1 Motor Enable 2 Motor Enable 3 Drive Select DMAEN |
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