PC87309VLJ datasheet(61/192 Pages) NSC

61 / 192 page

The Floppy Disk Controller (FDC) (Logical Device 0)

www.national.com

0: Use the TMR = 0 group of values. (Default)

1: Use the TMR = 1 group of values.

Third Command Phase Byte

Bit 4 - RECALIBRATE Step Pulses (R255)

This bit determines the maximum number of RECALI-

BRATE step pulses the controller issues before termi-

nating with an error, depending on the value of the

Extended Track Range (ETR) bit, i.e., bit 0 of the sec-

ond command phase byte in the MODE command.

A software reset clears this bit to its default value of 0.

0: If ETR (bit 0) = 0, the controller issues a maximum

of 85 recalibration step pulses.

If ETR (bit 0) = 1, the controller issues a maximum

of 3925 recalibration step pulses. (Default)

1: If ETR (bit 0) = 0, the controller issues a maximum

of 255 recalibration step pulses.

If ETR (bit 0) = 1, the controller issues a maximum

of 4095 recalibration step pulses.

Bit 5 - Burst Mode Disable (BST)

This bit enables or disables burst mode, if the FIFO is

enabled (bit 5 in the CONFIGURE command is 0). If the

FIFO is not enabled in the CONFIGURE command, then

the value of this bit is ignored.

A software reset enables burst mode, i.e., clears this bit

to its default value of 0, if the LOCK bit (bit 7 of the op-

code of the LOCK command) is 0. If it is 1, BST retains

its value after a software reset.

0: Burst mode enabled for FIFO execution phase data

transfers. (Default)

1: Burst mode disabled.

The FDC issues one DRQ or IRQ6 pulse for each

byte to be transferred while the FIFO is enabled.

Bit 6 - FIFO Read Disable (FRD)

This bit enables or disables the FIFO for microprocessor

read transfers from the controller, if the FIFO is enabled

(bit 5 in the CONFIGURE command is 0). If the FIFO is

not enabled in the CONFIGURE command, then the val-

ue of this bit is ignored.

A software reset enables the FIFO for reads, i.e., clears

this bit to its default value of 0, if the LOCK bit (bit 7 of

the opcode of the LOCK command) is 0. If it is 1, FRD

retains its value after a software reset.

0: Enable FIFO. Execution phase of microprocessor

read transfers use the internal FIFO. (Default)

1: Disable FIFO. All read data transfers take place

without the FIFO.

Bit 7 - FIFO Write Enable or Disable (FWR)

This bit enables or disables write transfers to the con-

troller, if the FIFO is enabled (bit 5 in the CONFIGURE

command is 0). If the FIFO is not enabled in the CON-

FIGURE command, then the value of this bit is ignored.

A software reset enables the FIFO for writes, i.e., clears

this bit to its default value of 0, if the LOCK bit (bit 7 of

the opcode of the LOCK command) is 0. If it is 1, FWR

retains its value after a software reset.

0: Enable FIFO. Execution phase microprocessor

write transfers use the internal FIFO. (Default)

1: Disable FIFO. All write data transfers take place

without the FIFO.

Fourth Command Phase Byte

Bits 3-0 - Head Settle Factor

This field is used to specify the maximum time allowed

for the read/write head to settle after a seek during an

implied seek operation.

The value specified by these bits (the head settle factor)

is multiplied by the multiplier for selected data rate to

specify a head settle time that is within the range for that

data rate.

Use the following formula to determine the head settle

factor that these bits should specify:

Head Settle Factor x Multiplier = Head Settle Time

TABLE 3-12 on page 61 shows the multipliers and head

settle time ranges for each data transfer rate. The de-

fault head settle factor, i.e., value for these bits, is 8.

TABLE 3-12. Multipliers and Head Settle Time Ranges

for Different Data Transfer Rates

Bit 4 - Scan Wild Card (WLD)

This bit determines whether or not a value of FFh from

either the microprocessor or the disk is recognized dur-

ing a scan command as a wildcard character.

0: A value of FFh from either the microprocessor or

the disk during a scan command is interpreted as a

wildcard character that always matches. (Default)

1: The scan commands do not recognize a value of

FFh as a wildcard character.

Bit 5 - CMOS Disk Interface Buffer Enable (BFR)

This bit configures drive output signals.

0: Drive output signals are conﬁgured as standard 4

mA push-pull output signals (40 mA sink, 4 mA

source). (Default)

1: Drive output signals are conﬁgured as 40 mA open-

drain output signals.

Bits 7,6 - Density Select Pin Conﬁguration (DENSEL)

This field can configure the polarity of the Density Select

output signal (DENSEL) as always low or always high,

as shown in Table 4-3. This allows the user more flexi-

bility with new drive types.

This field overrides the DENSEL polarity defined by the

DENSEL polarity bit of the SuperI/O FDC conﬁguration

page 30.

00: The DENSEL signal is always low.

01: The DENSEL signal is always high.

10: The DENSEL signal is undeﬁned.

Data Transfer

Rate (Kbps)

Multiplier

Head Settle

Time Range (msec)

250

0 - 120

300

6.666

0 - 100

500

0 - 60

1000

0 - 30

PC87309VLJ 数据表(PDF) 61 Page - National Semiconductor (TI)

PC87309VLJ 数据表(HTML) 61 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载