PC87309VLJ datasheet(92/192 Pages) NSC

92 / 192 page

Parallel Port (Logical Device 1)

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Bit 2 - ECP Interrupt Service

This bit enables servicing of interrupt requests. It is set

to 1 upon reset, and by the occurrence of interrupt

events. It is set to 0 by software.

While this bit is 1, neither the DMA nor the interrupt

events listed below will generate an interrupt.

While this bit is 0, the interrupt setup is “armed” and an

interrupt is generated on occurrence of an interrupt

event.

While the ECP clock is frozen, this bit always returns a

0 value, although it retains its proper value and may be

modified.

When one of the following interrupt events occurs while

this bit is 0, an interrupt is generated and this bit is set

to 1 by hardware.

— DMA is enabled (bit 3 of ECR is 1) and terminal

count is reached.

— FIFO write threshold reached (no DMA - bit 3 of ECR

is 0; forward direction (bit 5 of DCR is 0), and there

are eight or more bytes free in the FIFO).

— FIFO read threshold reached (no DMA - bit 3 of ECR

is 0; read direction set - bit 5 of DCR is 1, and there

are eight or more bytes to read from the FIFO).

0: The DMA and the above interrupts are not dis-

abled.

1: The DMA and the above three interrupts are dis-

abled.

Bit 3 - ECP DMA Enable

0: The DMA request signal (DRQ3-0) is set to TRI-

STATE and the appropriate acknowledge signal

(DACK3-0) is assumed inactive.

1: The DMA is enabled and the DMA starts when bit 2

of ECR is 0.

Bit 4 - ECP Interrupt Mask

0: An interrupt is generated on ERR assertion (the

high-to-low edge of ERR). An interrupt is also gen-

erated while ERR is asserted when this bit is

changed from 1 to 0; this prevents the loss of an in-

terrupt between ECR read and ECR write.

1: No interrupt is generated.

Bits 7-5 - ECP Mode Control

These bits set the mode for the ECP device. See Sec-

tion 4.6 "DETAILED ECP MODE DESCRIPTIONS" on

page 95 for a more detailed description of operation in

each of these ECP modes. The ECP modes are listed in

TABLE 4-9 "ECP Modes Encoding" and described in

detail in TABLE 4-11 "ECP Modes" on page 96.

TABLE 4-9. ECP Modes Encoding

4.5.13

ECP Extended Index Register (EIR)

The parallel port is partially configured by bits within the log-

ical device address space. These configuration bits are ac-

cessed via this read/write register and the Extended Data

Parallel Port Configuration register at index F0h of Logical

Device 1 is set to 1. See Section 2.6 on page 30.

The configuration bits within the parallel port address space

are initialized to their default values on reset, and not when

the parallel port is activated.

Bits 2-0 - Second Level Offset

Data written to these bits is used as a second level off-

set for accesses to a specific control register. Second

level offsets of 00h, 02h, 04h and 05h are supported. At-

tempts to access registers at any other offset have no

effect.

TABLE 4-10. Second Level Offsets

000:Access the Control0 register.

010:Access the Control2 register.

100:Access the Control4 register.

101:Access the PP Confg0 register.

ECR Bit Encoding

Mode Name

Bit 7

Bit 6

Bit 5

Standard

PS/2

Parallel Port FIFO

ECP FIFO

EPP Mode

FIFO Test

Conﬁguration

Second Level

Offset

Control

Described in

Section

00h

Control0

4.5.16

02h

Control2

4.5.17

04h

Control4

4.5.18

05h

PP Confg0

4.5.19

76543210

Reset

Required

ECP Extended Index

Offset 403h

Second Level Offset

Reserved

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