PC87309VLJ datasheet(103/192 Pages) NSC

103 / 192 page

Enhanced Serial Port with IR -UART2 (Logical Device 2)

103

www.national.com

The register bank organization enables access to the banks

as required for activation of all module modes, while main-

taining transparent compatibility with 16450 or 16550 soft-

ware, which activates only the registers and specific bits

used in those devices. For details, See Section 5.4.

The Bank Selection Register (BSR) selects the active bank

and is common to all banks. See Figure 5-1. Therefore,

each bank defines seven new registers.

FIGURE 5-1. Register Bank Architecture

The default bank selection after system reset is 0, which

places the module in the UART 16550 mode. Additionally,

setting the baud in bank 1 (as required to initialize the 16550

UART) switches the module to a Non-Extended UART

mode. This ensures that running existing 16550 software

will switch the system to the 16550 configuration without

software modification.

Table 5-1 shows the main functions of the registers in each

bank. Banks 0-3 control both UART and infrared modes of

operation; banks 4-7 control and configure the infrared

modes only.

TABLE 5-1. Register Bank Summary

Banks 0 and 1 are the 16550 register banks. The registers

in these banks are equivalent to the registers contained

in the 16550 UARTs and are accessed by 16550 soft-

ware drivers as if the module was a 16550. Bank 1 con-

tains the legacy Baud Generator Divisor Ports. Bank 0

registers control all other aspects of the UART function,

including data transfers, format setup parameters, inter-

rupt setup and status monitoring.

Bank 2 contains the non-legacy Baud Generator Divisor

Ports, and controls the extended features special to this

UART, that are not included in the 16550 repertoire.

These include DMA usage. See ”Extended UART

Mode” on page 104.

Bank 3 contains the Module Revision ID and shadow regis-

ters. The Module Revision ID (MRID) register contains

a code that identifies the revision of the module when

read by software. The shadow registers contain the

identical content as reset-when-read registers within

bank 0. Reading their contents from the shadow regis-

ters lets the system read the register content without re-

setting them.

Bank 4 contains setup parameters for the Infra-red modes.

Bank 5 registers control infrared parameters related to the

logical system I/O parameters.

Bank 6 registers control physical characteristics involved

in infrared communications (e.g. pulse width selection).

Bank 7 registers are dedicated to Consumer-IR configura-

tion and control.

BANK 0

BANK 1

BANK 2

BANK 3

BANK 4

BANK 5

BANK 6

BANK 7

Offset 07h

Offset 06h

Offset 05h

Offset 04h

LCR/BSR

Offset 02h

Offset 01h

Offset 00h

Common

Throughout

All Banks

16550 Banks

Bank

UART

Mode

Main Functions

Global Control and Status

Legacy Bank

Baud Generator Divisor,

Extended Control and Status

Module Revision ID and

Shadow Registers

IR mode setup

Infrared Control

Infrared Physical Layer

Conﬁguration

Consumer-IR and Optical

Transceiver Conﬁguration

PC87309VLJ 数据表(PDF) 103 Page - National Semiconductor (TI)

PC87309VLJ 数据表(HTML) 103 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载