PC87309VLJ datasheet(164/192 Pages) NSC

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Interrupt and DMA Mapping

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9.0

Interrupt and DMA Mapping

The standard Plug and Play configuration registers map

IRQs and DMA channels for the PC87309. See TABLES

2-7 "Plug and Play (PnP) Interrupt Configuration Registers"

and 2-8 "Plug and Play (PnP) DMA Configuration Regis-

ters" on page 24.

9.1

IRQ MAPPING

The PC87309 allows connection of some logical devices to

the seven IRQ signals.

The polarity of an IRQ signal is controlled by bit 1 of the In-

terrupt Type registers (index 71h) of each logical device.

The same bit also controls selection of push-pull or open-

drain IRQ output. High polarity implies push-pull output.

Low polarity implies open-drain output with strong pull-up

for a short time, followed by weak pull-up.

The IRQ input signals of the KBC or mouse, and of the par-

allel port are not affected by this bit, i.e., bit 1 at index 71h

of each logical device. This bit affects only the output buffer,

not the input buffer.

Only the UART1 and UART2 may map more than one logi-

cal device to any IRQ signal. Other devices may not do so.

An IRQ signal is in TRI-STATE when any of the following

conditions is true:

No logical device is mapped to the IRQ signal.

The logical device mapped to the IRQ signal is inactive.

The logical device mapped to the IRQ signal floats its

IRQ signal.

9.2

DMA MAPPING

Although the PC87309 allows some logical devices to be

connected to the three 8-bit DMA channels, it is illegal to

map two logical devices to the same pair of DMA signals.

A DRQ signal is in TRI-STATE and the DACK input signal

is blocked to 1 when any of the following conditions is true:

No logical device is mapped to the DMA channel.

The logical device mapped to the DMA channel is inactive.

The logical device mapped to the DMA channel floats its

DRQ signal.

PC87309VLJ 数据表(PDF) 164 Page - National Semiconductor (TI)

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