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PC87309VLJ 数据表(PDF) 185 Page - National Semiconductor (TI) |
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PC87309VLJ 数据表(HTML) 185 Page - National Semiconductor (TI) |
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185 / 192 page ![]() Device Specifications 185 www.national.com 10.3.17 Standard Parallel Port Timing Compatible Mode Extended Mode Typical Data Exchange Symbol Parameter Conditions Typ Max Unit tPDH Port Data Hold These times are system dependent and are therefore not tested. 500 nsec tPDS Port Data Setup These times are system dependent and are therefore not tested. 500 nsec tPILa Port Active Low Interrupt, Active 33 nsec tPILia Port Active Low Interrupt, Inactive 33 nsec tPIHa Port Active High Interrupt, Active 33 nsec tPIHia Port Active High Interrupt, Inactive 33 nsec tPIz Port Active High Interrupt, TRISTATE 33 nsec tSW Strobe Width These times are system dependent and are therefore not tested. 500 nsec tPILa tPILia ACK IRQ tPIHa tPIHia tPIHa tPIz ACK IRQ RD STR WR CTR4 = 0 (TRI-STATE) tPDS tPDH tSW BUSY ACK PD7-0 STB |
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