EM357-RTR datasheet(104/241 Pages) SILABS

104 / 241 page

Rev 1.3

104

SC1_TXBEGA: Address: 0x4000C810 Reset: 0x20000000



SC2_TXBEGA: Address: 0x4000C010 Reset: 0x20000000

SC_RXOVFA

[4]

This bit is set when DMA receive buffer A was passed an overrun error from the receive

FIFO. Neither receive buffer was capable of accepting any more bytes (unloaded), and the

FIFO filled up. Buffer A was the next buffer to load, and when it drained the FIFO the over-

run error was passed up to the DMA and flagged with this bit. Cleared the next time buffer

A is loaded and when the receive DMA is reset.

SC_TXACTB

[3]

This bit is set when DMA transmit buffer B is active.

SC_TXACTA

[2]

This bit is set when DMA transmit buffer A is active.

SC_RXACTB

[1]

This bit is set when DMA receive buffer B is active.

SC_RXACTA

[0]

This bit is set when DMA receive buffer A is active.



SC1_TXBEGA: Transmit DMA Begin Address Register A



SC2_TXBEGA: Transmit DMA Begin Address Register A

Bit

Name

Bit

Name

Bit

Name

SC_TXBEGA

Bit

Name

SC_TXBEGA

Bitname

Bitfield

Access

Description

SC_TXBEGA

[13:0]

DMA transmit buffer A start address.

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