EM357-RTR datasheet(129/241 Pages) SILABS

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9.3.7. Forced Output Mode

In output mode (CCyS bits = 00 in the TIMx_CCMR1 register), software can force each output compare signal

(OCyREF and then OCy) to an active or inactive level independently of any comparison between the output

compare register and the counter.

To force an output compare signal (OCyREF/OCy) to its active level, write 101 in the TIM_OCyM bits in the

corresponding TIMx_CCMR1 register. OCyREF is forced high (OCyREF is always active high) and OCy gets the

opposite value to the TIM_CCyP polarity bit. For example, TIM_CCyP = 0 defines OCy as active high, so when

OCyREF is active, OCy is also set to a high level.

The OCyREF signal can be forced low by writing the TIM_OCyM bits to 100 in the TIMx_CCMR1 register.

The comparison between the TIMx_CCRy shadow register and the counter is still performed and allows the

INT_TIMxCCRyIF flag to be set. Interrupt requests can be sent accordingly. This is described in “9.3.8. Output

Compare Mode” .

9.3.8. Output Compare Mode

This mode is used to control an output waveform or to indicate when a period of time has elapsed.

When a match is found between the capture/compare register and the counter, the output compare function:



Assigns the corresponding output pin to a programmable value defined by the output compare mode (the

TIM_OCyM bits in the TIMx_CCMR1 register) and the output polarity (the TIM_CCyP bit in the

TIMx_CCER register). The output can be frozen (TIM_OCyM = 000), be set active (TIM_OCyM = 001), be

set inactive (TIM_OCyM = 010), or can toggle (TIM_OCyM = 011) on the match.



Sets a flag in the interrupt flag register (the INT_TIMCCyIF bit in the INT_TIMxFLAG register).



Generates an interrupt if the corresponding interrupt mask is set (the TIM_CCyIF bit in the INT_TIMxCFG

The TIMx_CCRy registers can be programmed with or without buffer registers using the TIM_OCyBE bit in the

TIMx_CCMR1 register.

In output compare mode, the UEV has no effect on OCyREF or the OCy output. The timing resolution is one count

of the counter. Output compare mode can also be used to output a single pulse (in one pulse mode).

Procedure:

1. Select the counter clock (internal, external, and prescaler).

2. Write the desired data in the TIMx_ARR and TIMx_CCRy registers.

3. Set the INT_TIMCCyIF bit in INT_TIMxCFG if an interrupt request is to be generated.

4. Select the output mode. For example, you must write TIM_OCyM = 011, TIM_OCyBE = 0, TIM_CCyP = 0

and TIM_CCyE = 1 to toggle the OCy output pin when TIMx_CNT matches TIMx_CCRy, TIMx_CCRy

buffer is not used, OCy is enabled and active high.

5. Enable the counter: Set the TIM_CEN bit in the TIMx_CR1 register.

To control the output waveform, software can update the TIMx_CCRy register at any time, provided that the buffer

An example is given in Figure 9.21.

EM357-RTR 数据表(PDF) 129 Page - Silicon Laboratories

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