EM357-RTR datasheet(137/241 Pages) SILABS

137 / 241 page

137

Rev 1.3

9.3.13.2. Slave Mode: Gated Mode

In gated mode the counter is enabled depending on the level of a selected input.

In the following example, the up-counter counts only when the TI1 input is low:



Configure channel 1 to detect low levels on TI1:



Configure the input filter duration. In this example, no filter is required, so TIM_IC1F = 0000.



The capture prescaler is not used for triggering, so it is not configured.



The TIM_CC1S bits select the input capture source only, TIM_CC1S = 01 in the TIMx_CCMR1 register.



Write TIM_CC1P = 1 in the TIMx_CCER register to validate the polarity (and detect low level only).



Configure the timer in gated mode: Write TIM_SMS = 101 in the TIMx_SMCR register.



Select TI1 as the input source by writing TIM_TS = 101 in the TIMx_SMCR register.



Enable the counter: Write TIM_CEN = 1 in the TIMx_CR1 register. In gated mode, the counter does not

start if TIM_CEN = 0, regardless of the trigger input level.

The counter starts counting on the internal clock as long as TI1 is low and stops as soon as TI1 becomes high. The

INT_TIMTIF flag in the INT_TIMxFLAG register is set when the counter starts and when it stops. The delay

between the rising edge on TI1 and the actual stop of the counter is due to the resynchronization circuit on the TI1

input.

Figure 9.28 shows the counter in gated mode with counting enabled when TI1 is low.

Figure 9.28. Control Circuit in Gated Mode

9.3.13.3. Slave Mode: Trigger Mode

In trigger mode the counter starts in response to an event on a selected input.

In the following example, the up-counter starts in response to a rising edge on the TI2 input:



Configure channel 2 to detect rising edges on TI2:



Configure the input filter duration. In this example, no filter is required so TIM_IC2F = 0000.



The capture prescaler is not used for triggering, so it is not configured.



The TIM_CC2S bits select the input capture source only, TIM_CC2S = 01 in the TIMx_CCMR1 register.



Write TIM_CC2P = 0 in the TIMx_CCER register to validate the polarity and detect high level only.



Configure the timer in trigger mode: Write TIM_SMS = 110 in the TIMx_SMCR register.



Select TI2 as the input source by writing TIM_TS = 110 in the TIMx_SMCR register.

When a rising edge occurs on TI2, the counter starts counting on the internal clock and the INT_TIMTIF flag is set.

The delay between the rising edge on TI2 and the actual start of the counter is due to the resynchronization circuit

on the TI2 input.

Figure 9.29 illustrates the example in which the counter is started by a rising edge on TI2.

EM357-RTR 数据表(PDF) 137 Page - Silicon Laboratories

EM357-RTR 数据表(HTML) 137 Page - Silicon Laboratories

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载