EM357-RTR datasheet(142/241 Pages) SILABS

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Rev 1.3

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Figure 9.35. Triggering Timer 2 with Enable of Timer 1

9.3.14.4. Starting both Timers Synchronously in Response to an External Trigger

This example sets the enable of Timer 1 when its TI1 input rises, and the enable of Timer 2 with the enable of Timer

1. To ensure the counters are aligned, Timer 1 must be configured in master/slave mode (slave with respect to TI1,

master with respect to Timer 2):



Configure Timer 1 in master mode to send its Enable as trigger output: Write TIM_MMS = 001 in the

TIM1_CR2 register.



Configure Timer 1 slave mode to get the input trigger from TI1: Write TIM_TS = 100 in the TIM1_SMCR



Configure Timer 1 in trigger mode: Write TIM_SMS = 110 in the TIM1_SMCR register.



Configure the Timer 1 in master/slave mode: Write TIM_MSM = 1 in the TIM1_SMCR register.



Configure Timer 2 to get the input trigger from Timer 1: Write TIM_TS = 000 in the TIM2_SMCR register.



Configure Timer 2 in trigger mode: Write TIM_SMS = 110 in the TIM2_SMCR register.

When a rising edge occurs on TI1 (Timer 1), both counters start counting synchronously on the internal clock and

both timers’ INT_TIMTIF flags are set. Figure 9.36 shows this in operation.

Note:

In this example both timers are initialized before starting by setting their respective TIM_UG bits. Both counters starts

from 0, but an offset can be inserted between them by writing any of the counter registers (TIMx_CNT). The master/

slave mode inserts a delay between CNT_EN and CK_PSC on Timer 1.

EM357-RTR 数据表(PDF) 142 Page - Silicon Laboratories