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TNETV6446AINZWT 数据表(PDF) 176 Page - Texas Instruments |
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TNETV6446AINZWT 数据表(HTML) 176 Page - Texas Instruments |
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176 / 227 page  PCLK (Positive Edge Clocking) 13, 31 PCLK (Negative Edge Clocking) 11, 29 VCTL(A) A. VCTL = HSYNC, VSYNC, LCD_FIELD, and LCD_OE B. VDATA = COUT[7:0], YOUT[7:0], R[7:0], G[7:0], and B[7:0] VDATA(B) 14, 32 12, 30 VPBECLK TMS320DM6446 SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010 www.ti.com Table 6-62. Switching Characteristics Over Recommended Operating Conditions for VPBE Control and Data Output With Respect to PCLK and VPBECLK(1) (see Figure 6-52) -594 A-513 -810 NO. PARAMETER UNIT MIN MAX MIN MAX 11 td(PCLK-VCTLV) Delay time, PCLK edge to VCTL valid 13.3 13.3 ns 12 td(PCLK-VCTLIV) Delay time, PCLK edge to VCTL invalid 2 2 ns 13 td(PCLK-VDATAV) Delay time, PCLK edge to VDATA valid 13.6 13.3 ns 14 td(PCLK-VDATAIV) Delay time, PCLK edge to VDATA invalid 2 2 ns 29 td(VPBECLK-VCTLV) Delay time, VPBECLK rising edge to VCTL valid 13.3 13.3 ns 30 td(VPBECLK-VCTLIV) Delay time, VPBECLK rising edge to VCTL invalid 2 2 ns 31 td(VPBECLK-VDATAV) Delay time, VPBECLK rising edge to VDATA valid 13.6 13.3 ns 32 td(VPBECLK-VDATAIV) Delay time, VPBECLK rising edge to VDATA invalid 2 2 ns (1) PCLK may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode, the rising edge of PCLK is referenced. When in negative edge clocking mode, the falling edge of PCLK is referenced. Figure 6-52. VPBE Output Timing With Respect to PCLK and VPBECLK 176 Peripheral and Electrical Specifications Copyright © 2005–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6446 |
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