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TNETV6446AINZWT 数据表(PDF) 35 Page - Texas Instruments |
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TNETV6446AINZWT 数据表(HTML) 35 Page - Texas Instruments |
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35 / 227 page ![]() TMS320DM6446 www.ti.com SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010 Table 2-10. DDR2 Memory Controller Terminal Functions SIGNAL TYPE(1) OTHER(2) (3) DESCRIPTION NAME NO. DDR2 Memory Controller DDR_CLK0 W7 I/O/Z DVDDR2 DDR2 Clock DDR_CLK0 W8 I/O/Z DVDDR2 DDR2 Differential clock DDR_CKE V8 I/O/Z DVDDR2 DDR2 Clock Enable DDR_CS T9 I/O/Z DVDDR2 DDR2 Active low chip select DDR_WE T8 I/O/Z DVDDR2 DDR2 Active low Write enable DDR_DQM[3] T16 I/O/Z DVDDR2 DDR2 Data mask outputs DQM3: For upper byte data bus DDR_D[31:24] DDR_DQM[2] T14 I/O/Z DVDDR2 DQM2: For DDR_D[23:16] DDR_DQM[1] T6 I/O/Z DVDDR2 DQM1: For DDR_D[15:8] DQM0: For lower byte DDR_D[7:0] DDR_DQM[0] T4 I/O/Z DVDDR2 DDR_RAS U7 I/O/Z DVDDR2 DDR2 Row Access Signal output DDR_CAS T7 I/O/Z DVDDR2 DDR2 Column Access Signal output DDR_DQS[0] U4 I/O/Z DVDDR2 Data strobe input/outputs for each byte of the 32-bit data bus. They are outputs to the DDR2 memory when writing and inputs when reading. They are used to DDR_DQS[1] U6 I/O/Z DVDDR2 synchronize the data transfers. DDR_DQS[2] U14 I/O/Z DVDDR2 DQS3 : For upper byte DDR_D[31:24] DQS2: For DDR_D[23:16] DQS1: For DDR_D[15:8] DDR_DQS[3] U16 I/O/Z DVDDR2 DQS0: For bottom byte DDR_D[7:0] DDR_BS[0] U8 DDR_BS[1] V9 I/O/Z DVDDR2 Bank select outputs (BS[2:0]). Two are required to support 1Gb DDR2 memories. DDR_BS[2] U9 DDR_A[12] W9 DDR_A[11] W10 DDR_A[10] U10 DDR_A[9] U11 DDR_A[8] V10 DDR_A[7] V11 DDR_A[6] W11 I/O/Z DVDDR2 DDR2 address bus DDR_A[5] W12 DDR_A[4] V12 DDR_A[3] U12 DDR_A[2] V13 DDR_A[1] U13 DDR_A[0] W13 (1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal (2) Specifies the operating I/O supply voltage for each signal (3) For more information, see Section 5.2, Recommended Operating Conditions. Copyright © 2005–2010, Texas Instruments Incorporated Device Overview 35 Submit Documentation Feedback Product Folder Link(s): TMS320DM6446 |
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