TNETV6446AINZWT datasheet(41/227 Pages) TI1

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TMS320DM6446

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SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010

Table 2-17. USB Terminal Functions (continued)

SIGNAL

TYPE(1)

OTHER(2) (3)

DESCRIPTION

NAME

NO.

Core Power supply LDO output for USB phy. This must be connected via a 1-mF

capacitor to VSS.

USB_VDDA1P2LDO

G18

(3)

When the USB peripheral is not used, the USB_VDDA1P2LDO signal should still be

connected via a 1-mF capacitor to VSS.

Core Ground for USB phy. This is the ground for the LDO and must be connected to

VSS.

USB_VSSA1P2LDO

G17

GND

(3)

When the USB peripheral is not used, the USB_VSSA1P2LDO signal should still be

connected to VSS.

Table 2-18. VLYNQ Terminal Functions

SIGNAL

TYPE(1)

OTHER(2)

DESCRIPTION

NAME

NO.

VLYNQ

EM_CS5/

This pin is multiplexed between EMIFA, GPIO, and VLYNQ.

GPIO8/

I/O/Z

DVDD18

For VLYNQ, it is the clock (VLYNQ_CLOCK).

VLYNQ_CLOCK

EM_CS4/

This pin is multiplexed between EMIFA, GPIO, and VLYNQ.

GPIO9/

I/O/Z

DVDD18

For VLYNQ, it is the Serial Clock run request (VLYNQ_SCRUN).

VLYNQ_SCRUN

EM_A[15]/

This pin is multiplexed between EMIFA, GPIO, and VLYNQ.

GPIO16/

I/O/Z

DVDD18

For VLYNQ, it is transmit bus bit 3 output VLYNQ_TXD3.

VLYNQ_TXD3

EM_A[17]/

This pin is multiplexed between EMIFA, GPIO, and VLYNQ.

GPIO14/

I/O/Z

DVDD18

For VLYNQ, it is transmit bus bit 2 output VLYNQ_TXD2.

VLYNQ_TXD2

EM_A[19]/

This pin is multiplexed between EMIFA, GPIO, and VLYNQ.

GPIO12/

I/O/Z

DVDD18

For VLYNQ, it is transmit bus bit 1 output VLYNQ_TXD1.

VLYNQ_TXD1

EM_A[21]/

This pin is multiplexed between EMIFA, GPIO, and VLYNQ.

GPIO10/

I/O/Z

DVDD18

For VLYNQ, it is bit 0 of the transmit bus (VLYNQ_TXD0).

VLYNQ_TXD0

EM_A[14]/

This pin is multiplexed between EMIFA, GPIO, and VLYNQ.

GPIO17/

I/O/Z

DVDD18

For VLYNQ, it is receive bus bit 3 input VLYNQ_RXD3.

VLYNQ_RXD3

EM_A[16]/

This pin is multiplexed between EMIFA, GPIO, and VLYNQ.

GPIO15/

I/O/Z

DVDD18

For VLYNQ, it is receive bus bit 2 input VLYNQ_RXD2.

VLYNQ_RXD2

EM_A[18]/

This pin is multiplexed between EMIFA, GPIO, and VLYNQ.

GPIO13/

I/O/Z

DVDD18

For VLYNQ, it is receive bus bit 1 input VLYNQ_RXD1.

VLYNQ_RXD1

EM_A[20]/

This pin is multiplexed between EMIFA, GPIO, and VLYNQ.

GPIO11/

I/O/Z

DVDD18

For VLYNQ, it is receive bus bit 0 input VLYNQ_RXD0.

VLYNQ_RXD0

(1)

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal

(2)

Specifies the operating I/O supply voltage for each signal

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