TNETV6446AINZWT datasheet(86/227 Pages) TI1

86 / 227 page

TMS320DM6446

SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010

www.ti.com

5.2

Recommended Operating Conditions

MIN

NOM

MAX

UNIT

(-810 devices)

1.235

1.3

1.365

Supply voltage, Core (CVDD, CVDDDSP)

(1)

(A-513, -594

1.14

1.2

1.26

CVDD

devices)

Supply voltage, Core (VDDA1P1V,

(All devices)

1.14

1.2

1.26

USB_VDDA1P2LDO

(2)) (1)

Supply voltage, I/O, 3.3V (DVDD33, USB_DVDDA3P3)

3.15

3.3

3.45

DVDD

Supply voltage, I/O, 1.8V (DVDD18, DVDDR2, DDR_VDDDLL,

1.71

1.8

1.89

PLLVDD18, VDDA1P8V, USB_VDD1P8, MXVDD, M24VDD)

Supply ground (VSS, VSSA1P8V, VSSA1P1V, DDR_VSSDLL,

VSS

USB_VSSREF, USB_VSS1P8, USB_VSSA3P3, USB_VSSA1P2LDO,

MXVSS

(3), M24V

(3))

DDR_VREF

DDR2 reference voltage(4)

0.49DVDDR2

0.5DVDDR2

0.51DVDDR2

DDR_ZP

DDR2 impedance control, connected via 200

Ω resistor to VSS

VSS

DDR_ZN

DDR2 impedance control, connected via 200

Ω resistor to DVDDR2

DVDDR2

DAC_VREF

DAC reference voltage input

0.475

0.5

0.525

DAC_RBIAS

DAC biasing, connected via 4 k

Ω resistor to VSSA_1P8V

VSSA_1P8V

USB_VBUS

USB external charge pump input

4.75

5.25

High-level input voltage, I/O, 3.3V

VIH

High-level input voltage, non-DDR I/O, 1.8V

0.65DVDD

Low-level input voltage, I/O, 3.3V

0.8

VIL

Low-level input voltage, non-DDR I/O, 1.8V

0.35DVDD

Default (-594, -810)

°C

Operating case temperature

A version (A-513

-40

105

°C

device)

Default( -594)

600

MHz

Default (-810)

810

MHz

FSYSCLK1

DSP Operating Frequency (SYSCLK1)

A version (A-513

513

MHz

device)

(1)

Future variants of TI SOC devices may operate at voltages ranging from 0.9 V to 1.4 V to provide a range of system power/performance

options. TI highly recommends that users design-in a supply that can handle multiple voltages within this range (i.e., 1.0 V, 1.05 V,

1.1 V, 1.14 V, 1.2 V, 1.235 V, 1.26 V, 1.3 V, 1.365 V with ±3% tolerances) by implementing simple board changes such as reference

resistor values or input pin configuration modifications. Not incorporating a flexible supply may limit the system's ability to easily adapt to

future versions of TI SOC devices.

(2)

This pin is an internal LDO output and connected via 1 mF capacitor to USB_VSSA1P2LDO.

(3)

Oscillator ground must be kept separate from other grounds and connected directly to the crystal load capacitor ground.

(4)

DDR_VREF is expected to equal 0.5DVDDR2 of the transmitting device and to track variations in the DVDDR2.

Device Operating Conditions

Submit Documentation Feedback

Product Folder Link(s): TMS320DM6446

TNETV6446AINZWT 数据表(PDF) 86 Page - Texas Instruments

TNETV6446AINZWT 数据表(HTML) 86 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载