TNETV6446AINZWT datasheet(66/227 Pages) TI1

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TMS320DM6446

SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010

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3.4

Configurations at Reset

The following sections give information on configuration settings for the device at reset.

3.4.1

Device Configuration at Device Reset

Table 3-8 shows a summary of device inputs required for booting the ARM and DSP, and configuring

EMIFA data and address bus widths for proper operation of the device at the rising edge of the RESET

input.

Table 3-8. Device Configurations (Input Pins Sampled at Reset)

DEVICE SIGNALS

DEVICE SIGNAL NAME

SAMPLED

DESCRIPTION

AFTER RESET

AT RESET

BTSEL[1:0]

COUT[1:0]

ARM Boot mode selection pins.

‘00’ indicates ARM boots from ROM (NAND/SPI Flash).

‘01’ indicates that ARM boots from EMIFA (NOR Flash).

‘10’ indicates that the ARM boots from the HPI (ROM)

‘11’ indicates that ARM boots from ROM (UART0).

DSP_BT

COUT3

DSP Boot mode selection pin.

‘0’ sets ARM boot of C64x+.

‘1’ sets C64x+ self boot.

EM_WIDTH

COUT2

EMIFA data bus width selection pin.

‘0’ sets EMIFA to 8-bit data bus width

‘1’ sets EMIFA to 16-bit data bus width.

AEAW[4:0]

YOUT[4:0]

EMIFA address bus width selection pins for EMIFA address pins multiplexed with GPIO.

See the GPIO and EMIFA Multiplexing tables (Table 3-9, Table 3-10, and Table 3-11) for

details.

3.4.2

Peripheral Selection at Device Reset

As briefly mentioned in Table 3-8, the state of the AEAW[4:0] pins captured at reset configures the

number of EMIFA address pins required for device boot. These values are stored in the AEAW field of the

PINMUX0 register. At reset, this provides proper addressing for external boot. Unused address pins are

available for use as GPIO. The register settings are software programmable after reset. Table 3-9,

Table 3-10, and Table 3-11 show the AEAW[4:0] bit settings and the corresponding multiplexing for

EMIFA address and GPIO pins.

The number of EMIFA address bits enabled is configurable from 0 to 23. EM_BA[1] and EM_A[21:0] pins

that are not assigned to another peripheral and not enabled as address signals become GPIO pins. The

enabled address pins are always contiguous from EM_BA[1] upwards and address bits cannot be skipped.

The exception to this are the EM_A[2:1] pins. EM_A[2:1] are usable as the ALE and CLE signals for the

NAND Flash mode of EMIFA and are always enabled as EMIFA pins. If an address width of 0 is selected,

this still allows a NAND Flash to be accessed. Also, selecting an address width of 2, 3, or 4 (AEAW[4:0] =

00010, 00011, or 00100) always results in 4 address outputs. For these and other address bit enable

settings, see the GPIO and EMIFA Multiplexing tables (Table 3-9, Table 3-10, and Table 3-11).

Device Configurations

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