TNETV6446AINZWT datasheet(27/227 Pages) TI1

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TMS320DM6446

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SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010

2.7

Terminal Functions

The terminal functions tables (Table 2-5 through Table 2-30) identify the external signal names, the

associated pin (ball) numbers along with the mechanical package designator, the pin type, whether the pin

has any internal pullup or pulldown resistors, and a functional pin description. For more detailed

information on device configuration, peripheral selection, multiplexed/shared pins, see Section 3, Device

Configurations, of this data manual.

Table 2-5. BOOT Terminal Functions

SIGNAL

TYPE(1)

OTHER(2) (3)

DESCRIPTION

NAME

NO.

BOOT

These pins are multiplexed between ARM boot mode and

the VPBE. At reset, the boot mode inputs BTSEL0 and

BTSEL1 are sampled to determine the ARM boot

COUT0/

IPD

configuration. See below for the boot modes set by these

B3/

A16

I/O/Z

DVDD18

inputs. See Section 3.3, Bootmode, for more details.

BTSEL0

After reset, these are video encoder outputs COUT0 and

COUT1, or RGB666/888 Blue output data bits 3 and 4

B3/B4.

BTSEL1

BTSEL0

ARM Boot Mode

ARM ROM Boot (NAND, SPI)

COUT1/

[default]

IPD

B4/

B16

I/O/Z

DVDD18

ARM EMIFA Boot (NOR)

BTSEL1

ARM ROM Boot (HPI)

ARM ROM Boot (UART0)

This pin is multiplexed between EMIFA and the VPBE. At

reset, the input state is sampled to set the EMIFA data

COUT2/

bus width (EM_WIDTH). For an 8-bit-wide EMIFA data

IPD

B5/

A17

I/O/Z

bus, EM_WIDTH = 0. For a 16-bit-wide EMIFA data bus,

DVDD18

EM_WIDTH

EM_WIDTH = 1.

After reset, it is video encoder output COUT2 or

RGB666/888 Blue output data bit 5 B5.

This pin is multiplexed between DSP boot and the VPBE.

At reset, the input state is sampled to set the DSP boot

COUT3/

source DSP_BT. The DSP is booted by the ARM when

IPD

B6/

B17

I/O/Z

DSP_BT=0. The DSP boots from EMIFA when

DVDD18

DSP_BT

DSP_BT=1.

After reset, it is video encoder output COUT3 or

RGB666/888 Blue data bit 6 output B6.

YOUT0/

IPD

G5/

D15

I/O/Z

DVDD18

AEAW0

These pins are multiplexed between EMIFA and the

YOUT1/

VPBE. At reset, the input states of AEAW[4:0] are

IPD

G6/

D16

I/O/Z

sampled to set the EMIFA address bus width. See

DVDD18

AEAW1

Section 3.4.2, Peripheral Selection at Device Reset, for

details.

YOUT2/

After reset, these are video encoder outputs YOUT[0:4]

IPD

G7/

D17

I/O/Z

or RGB666/888 Red and Green data bit outputs G5, G6,

DVDD18

AEAW2

G7, R3, and R4.

YOUT3/

IPD

R3/

D18

I/O/Z

DVDD18

AEAW3

YOUT4/

IPD

R4/

E15

I/O/Z

DVDD18

AEAW4

(1)

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal

(2)

IPD = Internal pulldown, IPU = Internal pullup. (To pull up a signal to the opposite supply rail, a 1-k

Ω resistor should be used.)

(3)

Specifies the operating I/O supply voltage for each signal

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