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TNETV6446AINZWT 数据表(PDF) 81 Page - Texas Instruments |
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TNETV6446AINZWT 数据表(HTML) 81 Page - Texas Instruments |
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81 / 227 page  TMS320DM6446 www.ti.com SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010 As Table 3-32 shows, the UART0 pins are configurable for either UART0 transmit and receive data functions or for GPIO. Table 3-32. UART0 and GPIO Pin Multiplexing PINMUX1 REGISTER BIT MULTIPLEXED PINS FIELD UART_TXD0/ UART_RXD0/ UART0 GPIO[36] GPIO[35] 0 GPIO[36] GPIO[35] 1 UART_TXD0 UART_RXD0 3.5.6.10 HPI and EMIFA/ATA Pin Multiplexing When the HPIEN bit is set, the HPI module is given control of most of the EMIFA/ATA control pins as well as the EMIFA/ATA data bus. Table 3-33 shows which pins the HPI controls. HPIEN is set to 1 when the state of the BTSEL[1:0] pins = 10 is latched at the rising edge of reset. Also, this bit can be manipulated after reset by software. When the ATAEN bit is set and HPIEN is 0, the ATA mode of operation for pins shared with the HPI is available. EMIFA mode functionality for the shared HPI pins is set when both HPIEN and ATAEN are '0'. Table 3-33. HPI and EMIFA/ATA Pin Multiplexing PINMUX0 REGISTER MULTIPLEXED PINS BIT FIELDS HR/W/ HRDY/ HDS1/ HDS2/ HCNTLB/ HINT/ HD[15:0]/ HPI ATA HCS/ HHWIL/ HCNTLA/ INTRQ/ EM_WAIT/ DIOR/ DIOW/ ATA2/ ATA0/ DD[15:0]/ EN EN EM_CS2 EM_A[1] EM_A[2] EM_R/W IORDY EM_OE EM_WE EM_A[0] EM_BA[0] EM_D[15:0] 0 0 EM_CS2 EM_A[1](1) EM_R/W EM_WAIT EM_OE EM_WE EM_A[2](1) EM_A[0](1) EM_BA[0] EM_D[15:0] 0 1 EM_CS2 EM_A[1](1) INTRQ IORDY DIOR DIOW EM_A[2](1) EM_A[0](1) ATA0 DD[15:0] 1 - HCS HHWIL HR/W HRDY HDS1 HDS2 HCNTLA HCNTLB HINT HD[15:0] (1) This pin shares GPIO functionality and is set by AEAW[4:0] as shown in Table 3-12, Table 3-13, and Table 3-14. 3.6 Emulation Control The flexibility of the DM644x architecture allows either the ARM or DSP to control the various peripherals (setup registers, service interrupts, etc.). While this assignment is purely a matter of software convention, during an emulation halt it is necessary for the device to know which peripherals are associated with the halting processor so that only those modules receive the suspend signal. This allows peripherals associated with the other (unhalted) processor to continue normal operation. The SUSPSRC register indicates the emulation suspend source for those peripherals which support emulation suspend. The SUSPSRC register format is shown in Figure 3-9. Brief details on the peripherals which correspond to the register bits is given in Table 3-34. When the associated SUSPSRC bit is ‘0’, the peripheral’s emulation suspend signal is controlled by the ARM emulator and when set to ‘1’ it is controlled by the DSP emulator. Figure 3-9. Emulation Suspend Source Register (SUSPSRC) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 VICP VICP TIMR2 TIMR1 TIMR0 GPIO PWM2 PWM1 PWM0 SPI UART2 UART1 UART0 I2C ASP Rsvd SRC EN SRC SRC SRC SRC SRC SRC SRC SRC SRC SRC SRC SRC SRC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 15 13 12 11 10 9 8 6 5 4 0 HPI USB EMAC Rsvd Rsvd Rsvd Reserved SRC SRC SRC R-000 R/W-0 R-00 R/W-0 R-000 R/W-0 R-0 0000 LEGEND: R = Read, W = Write, n = value at reset Copyright © 2005–2010, Texas Instruments Incorporated Device Configurations 81 Submit Documentation Feedback Product Folder Link(s): TMS320DM6446 |
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