TNETV6446AINZWT datasheet(89/227 Pages) TI1

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TMS320DM6446

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SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010

6.1.1.2

Timing Parameters and Board Routing Analysis

The timing parameter values specified in this data manual do not include delays by board routings. As a

good board design practice, such delays must always be taken into account. Timing values may be

adjusted by increasing/decreasing such delays. TI recommends utilizing the available I/O buffer

information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS

models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing

Analysis application report (literature number SPRA839). If needed, external logic hardware such as

buffers may be used to compensate any timing differences.

For the DDR2 memory controller interface, it is not necessary to use the IBIS models to analyze timing

characteristics. TI provides a PCB routing rules solution that describes the routing rules to ensure the

DDR2 memory controller interface timings are met. See the Implementing DDR2 PCB Layout on the

TMS320DM644x DSP Application Report (literature number SPRAAC5).

6.2

Recommended Clock and Control Signal Transition Behavior

All clocks and control signals should transition between VIH and VIL (or between VIL and VIH) in a

monotonic manner.

6.3

Power Supplies

For more information regarding TI's power management products and suggested devices to power TI

DSPs, visit www.ti.com/dsppower.

6.3.1

Power-Supply Sequencing

The DM6446 includes two core supplies — CVDD and CVDDDSP, as well as three I/O supplies — DVDD18,

DVDDR2, and DVDD33. To ensure proper device operation, a specific power-up sequence must be followed.

The core supply power-up sequence is dependent on the DSP boot mode selected at reset. If the DSP

boot mode is configured as Self-Boot mode, then both core supplies must be powered up at the same

time.

If the DSP boot mode is configured as Host-Boot, where the ARM boots the DSP, the two core supplies

may be ramped simultaneously or powered up separately. When powered up separately, the CVDDDSP

supply must not be ramped prior to the CVDD supply. The CVDDDSP supply must be powered up before the

shorting switch is closed (enabled). Prior to powering up the CVDDDSP supply, it should be left floating and

not driven to ground. Table 6-1 and Figure 6-4 describe the power-on sequence timing requirements for

DSP Host-Boot mode.

To minimize the voltage difference between these two core supplies, a single regulator source must be

used to power the CVDD and CVDDDSP supplies.

For more information, see Section 3.2.1, Power Configurations at Reset.

Peripheral and Electrical Specifications

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