TNETV6446AINZWT datasheet(78/227 Pages) TI1

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TMS320DM6446

SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010

www.ti.com

3.5.6.5

VLYNQ, EMIFA, and GPIO Pin Multiplexing

Table 3-23 and Table 3-24 show the VLYNQ pin control and multiplexing. If VLYNQ is disabled

(VLYNQEN=0), the AECS5 and AECS4 bits select between the GPIO[8] / EMIFA EM_CS5 and GPIO[9] /

EMIFA EM_CS4 functions, and the AEAW field determines the partitioning between GPIO and the upper

EMIFA address pins. If VLYNQ is enabled (VLYNQEN=1), VLYNQ_CLOCK, VLYNQ_TXD0, and

VLYNQ_RXD0 are always selected. The VLYNQ_SCRUN function is only enabled if VLYNQEN=1 and

VLSCREN=1 (VLSCREN overrides AECS4). The remaining VLYNQ TX/RX pins are selected based on

the VLYNQWD value. Unselected VLYNQ TX/RX pins will function as either GPIO or EMIFA address

based on the AEAW value.

Table 3-23. VLYNQ Control, EMIFA, and GPIO Pin Multiplexing

PINMUX0 REGISTER BIT FIELDS

MULTIPLEXED PINS

EM_CS5/

EM_CS4/

VLYNQEN

VLSCREN

AECS5

AECS4

GPIO[8]/

GPIO[9]/

VLYNQ_CLOCK

VLYNQ_SCRUN

GPIO[8]

GPIO[9]

GPIO[8]

EM_CS4

EM_CS5

GPIO[9]

EM_CS5

EM_CS4

VLYNQ_CLOCK

GPIO[9]

VLYNQ_CLOCK

EM_CS4

VLYNQ_CLOCK

VLYNQ_SCRUN

Table 3-24. VLYNQ Data, EMIFA, and GPIO Pin Multiplexing

PINMUX0

MULTIPLEXED PINS

BIT FIELDS

EM_A[21]/

EM_A[20]/

EM_A[19]/

EM_A[18]/

EM_A[17]/

EM_A[16]/

EM_A[15]/

EM_A[14]/

VLYNQEN

VLYNQWD

GPIO[10]/

GPIO[11]/

GPIO[12]/

GPIO[13]/

GPIO[14]/

GPIO[15]/

GPIO[16]/

GPIO[17]/

VL_TXD0

VL_RXD0

VL_TXD1

VL_RXD1

VL_TXD2

VL_RXD2

VL_TXD3

VL_RXD3

EM_A[21]/

EM_A[20]/

EM_A[19]/

EM_A[18]/

EM_A[17]/

EM_A[16]/

EM_A[15]/

EM_A[14]/

GPIO[10](1)

GPIO[11](1)

GPIO[12](1)

GPIO[13](1)

GPIO[14](1)

GPIO[15](1)

GPIO[16](1)

GPIO[17](1)

VL_TXD0

VLRXD0

EM_A[19]/

EM_A[18]/

EM_A[17]/

EM_A[16]/

EM_A[15]/

EM_A[14]/

GPIO[12](1)

GPIO[13](1)

GPIO[14](1)

GPIO[15](1)

GPIO[16](1)

GPIO[17](1)

VL_TXD0

VLRXD0

VL_TXD1

VLRXD1

EM_A[17]/

EM_A[16]/

EM_A[15]/

EM_A[14]/

GPIO[14](1)

GPIO[15](1)

GPIO[16](1)

GPIO[17](1)

VL_TXD0

VLRXD0

VL_TXD1

VLRXD1

VL_TXD2

VLRXD2

EM_A[15]/

EM_A[14]/

GPIO[16](1)

GPIO[17](1)

VL_TXD0

VLRXD0

VL_TXD1

VLRXD1

VL_TXD2

VLRXD2

VL_TXD3

VLRXD3

(1)

This pin shares GPIO functionality set by AEAW[4:0] as shown in Table 3-9.

Device Configurations

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