TNETV6446AINZWT datasheet(97/227 Pages) TI1

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TMS320DM6446

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SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010

Table 6-6. PSC Register Memory Map (continued)

HEX ADDRESS RANGE

DESCRIPTION

ACRONYM

0x01C4 1000

MPFAR

Memory Protection Fault Address Register

0x01C4 1004

MPFSR

Memory Protection Fault Status Register

0x01C4 1008

MPFCR

Memory Protection Fault Command Register

0x01C4 100C

MPAA

Memory Protection Page Attribute Register

0x01C4 1010 - 0x01C4 1FFF

Reserved

6.4

Reset

DM6446 supports various types of resets. Power-on-reset (POR), warm reset, max reset, system reset,

C64x+ local reset, and module reset are summarized in Table 6-7.

Table 6-7. DM6446 Resets

Type

Initiator

Description

Power-on-reset (POR)

RESET pin active low while TRST is low.

Global chip reset (Cold reset). Activates the POR signal

on chip, which is used to reset test and emulation logic.

Warm reset

RESET pin active low while TRST is high.

Resets everything except for test and emulation logic.

ARM emulator stays alive during warm reset, but the

C64x+ emulator does not.

Maximum reset

Emulator, WD Timer

Same as Warm reset, except for initiators.

C64x+ Local reset

Software (register bit)

MMR controls the C64x+ reset input. This is used for

control of C64x+ reset by the ARM. The C64x+ Slave

DMA port is still alive when in local reset.

Power-on-reset (POR) is the global chip reset and it affects test, emulation, and other circuitry. It is

invoked by driving the RESET pin active low while TRST is held low. A POR is required to place DM6446

into a known good initial state. POR can be asserted prior to ramping the core and I/O voltages or after

the core and I/O voltages have reached their proper operating conditions. As a best practice, RESET

should be asserted (held low) during power-up. Prior to deasserting RESET (low-to-high transition), the

core and I/O voltages should be at their proper operating conditions and if an external 27 MHz oscillator is

used on the MXI/CLKIN pin, the external clock should also be running at the correct frequency.

Warm reset is activated by driving the RESET pin active low, while TRST is inactive high. This does not

reset test or ARM emulation logic. An ARM emulator session will stay alive during warm reset, but a

C64x+ emulator session will not.

Maximum reset is initiated by the emulator or the watchdog timer and the reset effects are the same as a

warm reset. The emulator initiates a maximum reset via the ICEPICK module. When the watchdog timer

counter reaches zero, this will initiate a maximum reset to recover from a runaway condition. Both of the

maximum reset initiators can be masked by the ARM emulator.

System reset is initiated by the emulator and is a soft reset. Memory contents are maintained. Test,

emulation, clock, and power control logic are unaffected. The emulator initiates a system reset via the

C64x+ emulation logic, or through ICECRUSHER. Both of these reset initiators are non-maskable resets.

The C64x+ DSP has an internal reset input that allows a host to control it. This reset is configured through

a MMR bit (MDCTL[39].LRSTz) in the PSC module. When in C64x+ local reset, the slave DMA port on

C64x+ will remain active and the internal memory will be accessible, including access to the VICP memory

through the L2 port (UMAP port).

For details on reset control/status registers, see the TMS320DM644x DMSoC ARM Subsystem Reference

Guide (literature number SPRUE14).

For information on peripheral selection at the rising edge of RESET, see Section 3, Device Configurations,

of this data manual.

Peripheral and Electrical Specifications

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