TNETV6446AINZWT datasheet(12/227 Pages) TI1

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TMS320DM6446

SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010

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Invalidate entire TLB, using CP15 register 8

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Invalidate TLB entry, selected by MVA, using CP15 register 8

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Lockdown of TLB entries, using CP15 register 10

2.3.4

Caches and Write Buffer

The size of the Instruction Cache is 16KB, Data cache is 8KB. Additionally, the Caches have the following

features:

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Virtual index, virtual tag, and addressed using the Modified Virtual Address (MVA)

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Four-way set associative, with a cache line length of eight words per line (32-bytes per line) and with

two dirty bits in the Dcache

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Dcache supports write-through and write-back (or copy back) cache operation, selected by memory

region using the C and B bits in the MMU translation tables.

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Critical-word first cache refilling

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Cache lockdown registers enable control over which cache ways are used for allocation on a line fill,

providing a mechanism for both lockdown, and controlling cache corruption

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Dcache stores the Physical Address TAG (PA TAG) corresponding to each Dcache entry in the TAG

RAM for use during the cache line write-backs, in addition to the Virtual Address TAG stored in the

TAG RAM. This means that the MMU is not involved in Dcache write-back operations, removing the

possibility of TLB misses related to the write-back address.

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Cache maintenance operations provide efficient invalidation of, the entire Dcache or Icache, regions of

the Dcache or Icache, and regions of virtual memory.

The write buffer is used for all writes to a noncachable bufferable region, write-through region and write

misses to a write-back region. A separate buffer is incorporated in the Dcache for holding write-back for

cache line evictions or cleaning of dirty cache lines. The main write buffer has 16-word data buffer and a

four-address buffer. The Dcache write-back has eight data word entries and a single address entry.

2.3.5

Tightly Coupled Memory (TCM)

ARM internal RAM is provided for storing real-time and performance-critical code/data and the Interrupt

Vector table. ARM internal ROM enables non-EMIFA boot options, such as NAND and UART. The RAM

and ROM memories interfaced to the ARM926EJ-S via the tightly coupled memory interface that provides

for separate instruction and data bus connections. Since the ARM TCM does not allow instructions on the

D-TCM bus or data on the I-TCM bus, an arbiter is included so that both data and instructions can be

stored in the internal RAM/ROM. The arbiter also allows accesses to the RAM/ROM from extra-ARM

sources (e.g., EDMA3 or other masters). The ARM926EJ-S has built-in DMA support for direct accesses

to the ARM internal memory from a non-ARM master. Because of the time-critical nature of the TCM link

to the ARM internal memory, all accesses from non-ARM devices are treated as DMA transfers.

Instruction and Data accesses are differentiated via accessing different memory map regions, with the

instruction region from 0x0000 through 0x7FFF and data from 0x8000 through 0xFFFF. The instruction

region at 0x0000 and data region at 0x8000 map to the same physical 16KB TCM RAM. Placing the

instruction region at 0x0000 is necessary to allow the ARM Interrupt Vector table to be placed at 0x0000,

as required by the ARM architecture. The internal 16-KB RAM is split into two physical banks of 8KB

each, which allows simultaneous instruction and data accesses to be accomplished if the code and data

are in separate banks.

2.3.6

Advanced High-Performance Bus (AHB)

The ARM Subsystem uses the AHB port of the ARM926EJ-S to connect the ARM to the Config bus and

the external memories. Arbiters are employed to arbitrate access to the separate D-AHB and I-AHB by the

Config Bus and the external memories bus.

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