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TNETV6446AINZWT 数据表(PDF) 84 Page - Texas Instruments

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部件名 TNETV6446AINZWT
功能描述  Digital Media System-on-Chip
PDF  227 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

TNETV6446AINZWT 数据表(HTML) 84 Page - Texas Instruments

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SCR5
SCR1
Bridge2
CF/ATA
VLYNQ
EMAC
USB2.0
SCR2
Bridge1
Bridge7
ARM
C64x+
L2Cache
VICP
Bridge6
Bridge5
SCR3
VPSS
EDMA3TC1
Bridge3
ARM
TCM
C64x+
L2/L1
DDR2Ctrl
(Mem/Reg)
SCR6
CF/ATA Reg
USBReg
EMACReg
EMACCtrlModReg
EMACCtrlModRAM
MDIO
VPSSReg
SPI0/1
GPIO
AINTC
SystemReg
PSC
PLLC0
PLLC1
Bridge9
Bridge8
SCR7
ASP
VLYNQ
MMC/SD
EMIFA/NAND
SCR8
UART0
UART1
UART2
I2C
PWM0
PWM1
PWM2
Timer0
Timer1
Timer2
SCR4
EDMA3CC
EDMA3TC0
EDMA3TC1
32
32
32
32
64
32
32
32
32
64
64
64
64
64
Read
Write
Read
Write
64
64
64
64
64
128
256
32
32
32
32
32
32
64
64
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
DSP/2ClockRate
DSP/3ClockRate
DSP/6ClockRate
EDMA3TC0
MXI/CLKINRate
32
32
HPI
32
HPI
32
TMS320DM6446
SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010
www.ti.com
4.1
System Interconnect Block Diagram
Figure 4-1 displays the DM6446 system interconnect block diagram. The following is a list that helps
interpret this diagram:
•
The direction of the arrows indicates either bus master or bus slave.
•
The arrow originates at a bus master and terminates at a bus slave.
•
The direction of the arrows does not indicate the direction of data flow. Data flow is typically
bi-directional for each of the documented bus paths.
•
The pattern of each arrow's line indicates the clock rate at which it is operating, either DSP/2, DSP/3,
or DSP/6 clock rate.
•
Some peripherals may have multiple instances shown in the diagram. A peripheral may have multiple
instances shown for a variety of reasons, some of which are described below:
–
The peripheral/module has master port(s) for data transfers, as well as slave port(s) for register
access, data access, and/or memory access. Examples of these peripherals are C64x+
megamodule, EDMA3, CF/ATA, USB, EMAC, VPSS, VLYNQ, and HPI.
–
The peripheral/module has a master port as well as slave memories. Examples of these are the
C64x+ megamodule and the ARM subsystem.
Figure 4-1. System Interconnect Block Diagram
84
System Interconnect
Copyright © 2005–2010, Texas Instruments Incorporated
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Product Folder Link(s): TMS320DM6446



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