| 数据搜索系统,热门电子元器件搜索 |
|
TNETV6446AINZWT 数据表(PDF) 31 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
TNETV6446AINZWT 数据表(HTML) 31 Page - Texas Instruments |
|
31 / 227 page ![]() TMS320DM6446 www.ti.com SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010 Table 2-9. EMIFA Terminal Functions (continued) SIGNAL TYPE(1) OTHER(2) (3) DESCRIPTION NAME NO. EM_A[13]/ This pin is multiplexed between EMIFA and GPIO. N4 I/O/Z DVDD18 GPIO18 For EMIFA, it is address bit 13 output EM_A[13]. EM_A[12]/ This pin is multiplexed between EMIFA and GPIO. R1 I/O/Z DVDD18 GPIO19 For EMIFA, it is address bit 12 output EM_A[12]. EM_A[11]/ This pin is multiplexed between EMIFA and GPIO. P2 I/O/Z DVDD18 GPIO20 For EMIFA, it is address bit 11 output EM_A[11]. EM_A[10]/ This pin is multiplexed between EMIFA and GPIO. P1 I/O/Z DVDD18 GPIO21 For EMIFA, it is address bit 10 output EM_A[10]. EM_A[9]/ This pin is multiplexed between EMIFA and GPIO. M4 I/O/Z DVDD18 GPIO22 For EMIFA, it is address bit 9 output EM_A[9]. EM_A[8]/ This pin is multiplexed between EMIFA and GPIO. N3 I/O/Z DVDD18 GPIO23 For EMIFA, it is address bit 8 output EM_A[8]. EM_A[7]/ This pin is multiplexed between EMIFA and GPIO. N2 I/O/Z DVDD18 GPIO24 For EMIFA, it is address bit 7 output EM_A[7]. EM_A[6]/ This pin is multiplexed between EMIFA and GPIO. N1 I/O/Z DVDD18 GPIO25 For EMIFA, it is address bit 6 output EM_A[6]. EM_A[5]/ This pin is multiplexed between EMIFA and GPIO. K3 I/O/Z DVDD18 GPIO26 For EMIFA, it is address bit 5 output EM_A[5]. EM_A[4]/ This pin is multiplexed between EMIFA and GPIO. K4 I/O/Z DVDD18 GPIO27 For EMIFA, it is address bit 4 output EM_A[4]. EM_A[3]/ This pin is multiplexed between EMIFA and GPIO. K2 I/O/Z DVDD18 GPIO28 For EMIFA, it is address bit 3 output EM_A[3]. EM_A[2]/ This pin is multiplexed between EMIFA and HPI. (CLE)/ J1 I/O/Z DVDD18 For EMIFA, this pin is the EM_A[2] address line. HCNTL0 EM_A[1]/ (ALE)/ J2 I/O/Z DVDD18 This pin is multiplexed between EMIFA (NAND/SmartMedia.xD) and HPI. HHWIL This pin is multiplexed between EMIFA, ATA/CF, HPI, and GPIO. EM_A[0]/ For EMIFA, this is Address output EM_A[0], which is the least significant bit on a DA2/ 32-bit word address. J4 I/O/Z DVDD18 HCNTL1/ When connected to a 16-bit asynchronous memory, this pin is the 2nd bit of the GPIO53 address. For an 8-bit asynchronous memory, this pin is the 3rd bit of the address. Copyright © 2005–2010, Texas Instruments Incorporated Device Overview 31 Submit Documentation Feedback Product Folder Link(s): TMS320DM6446 |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |