TNETV6446AINZWT datasheet(13/227 Pages) TI1

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TMS320DM6446

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SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010

2.3.7

Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)

To support real-time trace, the ARM926EJ-S processor provides an interface to enable connection of an

Embedded Trace Macrocell (ETM). The ARM926ES-J Subsystem in the DM6446 also includes the

Embedded Trace Buffer (ETB). The ETM consists of two parts:

•

Trace Port provides real-time trace capability for the ARM9.

•

Triggering facilities provide trigger resources, which include address and data comparators, counter,

and sequencers.

The DM6446 trace port is not pinned out and is instead only connected to the Embedded Trace Buffer.

The ETB has a 4KB buffer memory. ETB enabled debug tools are required to read/interpret the captured

trace data.

2.3.8

ARM Memory Mapping

The ARM memory map is shown in Section 2.5, Memory Map Summary, of this document. The ARM has

access to memories shown in the following sections.

2.3.8.1

ARM Internal Memories

The ARM has access to the following ARM internal memories:

•

16KB ARM Internal RAM on TCM interface, logically separated into two 8KB pages to allow

simultaneous access on any given cycle if there are separate accesses for code (I-TCM bus) and data

(D-TCM) to the different memory regions.

•

8KB ARM Internal ROM

2.3.8.2

External Memories

The ARM has access to the following external memories:

•

DDR2 Synchronous DRAM

•

Asynchronous EMIF / NOR Flash / NAND Flash

•

ATA/CF

•

Flash card devices:

–

MMC/SD with SDIO

–

SmartMedia

2.3.8.3

DSP Memories

The ARM has access to the following DSP memories:

•

L2 RAM

•

L1P RAM

•

L1D RAM

2.3.8.4

ARM-DSP Integration

DM6446 ARM and DSP integration features are as follows:

•

DSP visibility from ARM’s memory map, see Section 2.5, Memory Map Summary, for details

•

Boot Modes for DSP - see Section 3 (Device Configurations) and Section 3.3.3 (DSP Boot) for details

•

ARM control of DSP boot / reset - see Section 3 (Device Configurations) and Section 3.3.2 (ARM Boot)

for details

•

ARM control of DSP isolation and powerdown / powerup - see Section 3, Device Configurations, for

details

•

ARM and DSP Interrupts - see Section 6.7.1, ARM CPU Interrupts, and Section 6.7.2, DSP Interrupts,

for details

Device Overview

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