TNETV6446AINZWT datasheet(7/227 Pages) TI1

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TMS320DM6446

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SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010

Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

This data manual revision history highlights the technical changes made to the SPRS283G device-specific

data manual to make it an SPRS283H revision.

Scope: Added information/data on silicon revision 2.3.

Applicable updates to the DM644x device family, specifically relating to the TMS320DM6446 device, have

been incorporated.

TMS320DM6446 Revision History

SEE

ADDITIONS/MODIFICATIONS/DELETIONS

Global

•

Added information/data on silicon revision 2.3

Section 2.1

Table 2-1, Characteristics of the Processor:

Device Characteristics

•

Updated/changed "C64x+ Megamodule Revision" for silicon revision 2.3

•

Updated/changed "JTAG BSDL_ID" for silicon revision 2.3

Section 2.8.3.1

•

Updated/changed list of reference documents

Related Documentation

From Texas

Instruments

Section 3.3.1.1

•

Updated/changed the address of the BOOTCFG register from "0x01C4 000A" to "0x01C4 0014"

BOOTCFG Register

[Update made in Revision G]

Description

Section 3.3.3

•

Added Section 3.3.3.1, Host-Boot Mode

DSP Boot

Section 3.5.1

Figure 3-6, MSTPRI1 Register:

Switched Central

•

Updated/changed the default value of bits 22:20 from "R-100" to "R/W-100"

Resource (SCR) Bus

Priorities

Section 3.5.4

Figure 3-7, PINMUX0 Register:

PINMUX0 Register

•

Updated/changed the default value of bits 4:0 from "R/W-LLLL" to "R/W-LLLLL"

Description

Section 6.3.1.3

Figure 6-6, PLL1 and PLL2 Clock Domain Block Diagram:

DM6446 Power and

•

PLL Controller 2: Updated/changed "PLLDIV1 (/1)" to "PLLDIV1 (/10)"

Clock Domains

Section 6.6.3

Table 6-19, Switching Characteristics Over Recommended Operating Conditions for CLK_OUT1:

Clock PLL Electrical

•

Parameter 1 [tc]: Added "ns" in the UNIT column

Data/Timing (Input and

Output Clocks)

Section 6.10.1.2

Table 6-35, Switching Characteristics Over Recommended Operating Conditions for Asynchronous

EMIFA Electrical

Memory Cycles for EMIFA Module:

Data/Timing

•

Parameter 24 [tw(EMWEL)]: Added "ns" in the UNIT column

Section 6.12.1

Table 6-43, MMC/SD/SDIO Register Descriptions:

MMC/SD/SDIO

•

Updated/changed 0x01E1 0064 from "SDIO" to "SDIOCTL (SDIO Control Register)"

Peripheral

•

Updated/changed 0x01E1 0068 from "SDIO" to "SDIOST0 (SDIO Status Register 0)"

Description(s)

•

Updated/changed 0x01E1 006C from "SDIO" to "SDIOIEN (SDIO Interrupt Enable Register)"

•

Updated/changed 0x01E1 0070 from "Reserved" to "SDIOIST (SDIO Interrupt Status Register)"

Contents

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