TNETV6446AINZWT datasheet(4/227 Pages) TI1

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TMS320DM6446

SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010

www.ti.com

The DM6446 device includes a Video Processing Subsystem (VPSS) with two configurable video/imaging

peripherals: 1 Video Processing Front-End (VPFE) input used for video capture, 1 Video Processing

Back-End (VPBE) output with imaging co-processor (VICP) used for display.

The Video Processing Front-End (VPFE) is comprised of a CCD Controller (CCDC), a Preview Engine

(Previewer), Histogram Module, Auto-Exposure/White Balance/Focus Module (H3A), and Resizer. The

CCDC is capable of interfacing to common video decoders, CMOS sensors, and Charge Coupled Devices

(CCDs). The Previewer is a real-time image processing engine that takes raw imager data from a CMOS

sensor or CCD and converts from an RGB Bayer Pattern to YUV4:2:2. The Histogram and H3A modules

provide statistical information on the raw color data for use by the DM6446. The Resizer accepts image

data for separate horizontal and vertical resizing from 1/4x to 4x in increments of 256/N, where N is

between 64 and 1024.

The Video Processing Back-End (VPBE) is comprised of an On-Screen Display Engine (OSD) and a

Video Encoder (VENC). The OSD engine is capable of handling 2 separate video windows and 2 separate

OSD windows. Other configurations include 2 video windows, 1 OSD window, and 1 attribute window

allowing up to 8 levels of alpha blending. The VENC provides four analog DACs that run at 54 MHz,

providing a means for composite NTSC/PAL video, S-Video, and/or Component video output. The VENC

also provides up to 24 bits of digital output to interface to RGB888 devices. The digital output is capable of

8/16-bit BT.656 output and/or CCIR.601 with separate horizontal and vertical syncs.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the DM644x and

the network. The DM6446 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps)

and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS)

support.

The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to

enumerate all PHY devices in the system. Once a PHY candidate has been selected by the ARM, the

MDIO module transparently monitors its link state by reading the PHY status register. Link change events

are stored in the MDIO module and can optionally interrupt the ARM, allowing the ARM to poll the link

status of the device without continuously performing costly MDIO accesses.

The HPI, I2C, SPI, USB2.0, and VLYNQ ports allow DM6446 to easily control peripheral devices and/or

communicate with host processors. The DM6446 also provides multimedia card support, MMC/SD, with

SDIO support.

The DM6446 also includes a Video/Imaging Co-processor (VICP) to offload many video and imaging

processing tasks from the DSP core, making more DSP MIPS available for common video and imaging

algorithms. For more information on the VICP enhanced codecs, such as H.264 and MPEG4, please

contact your nearest TI sales representative.

The rich peripheral set provides the ability to control external peripheral devices and communicate with

external processors. For details on each of the peripherals, see the related sections later in this document

and the associated peripheral reference guides listed in Section 2.8.3.1, Related Documentation From

Texas Instruments.

The DM6446 has a complete set of development tools for both the ARM and DSP. These include C

compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™

debugger interface for visibility into source code execution.

Digital Media System-on-Chip (DMSoC)

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