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TNETV6446AINZWT 数据表(PDF) 42 Page - Texas Instruments

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部件名 TNETV6446AINZWT
功能描述  Digital Media System-on-Chip
PDF  227 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

TNETV6446AINZWT 数据表(HTML) 42 Page - Texas Instruments

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TMS320DM6446
SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010
www.ti.com
Table 2-19. VPFE Terminal Functions
SIGNAL
TYPE(1)
OTHER(2) (3)
DESCRIPTION
NAME
NO.
VIDEO/IMAGE IN (VPFE)
Pixel clock input used to load image data into the CCD Controller (CCDC) on pins
PCLK
M19
I
DVDD18
CI[7:0] and YI[7:0].
Vertical synchronization signal that can be either an input (slave mode) or an output
VD
L19
I/O/Z
DVDD18
(master mode), which signals the start of a new frame to the CCDC.
Horizontal synchronization signal that can be either an input (slave mode) or an
HD
M18
I/O/Z
DVDD18
output (master mode), which signals the start of a new line to the CCDC.
This pin is multiplexed between the CCDC and UART2.
When used by the CCDC as input CI7, it supports several modes.
CI7/
IPD
In 16-bit CCD Analog-Front-End (AFE) mode, it is input CCD15.
CCD15/
N19
I/O/Z
DVDD18
In 16-bit YCbCr mode, it is time multiplexed between CB7 and CR7 inputs.
UART_RXD2
In 8-bit YCbCr mode, it is time multiplexed between Y7, CB7, and CR7 of the upper
8-bit channel.
This pin is multiplexed between the CCDC and UART2.
When used by the CCDC as input CI6, it supports several modes. In 16-bit CCD
CI6/
IPD
AFE mode, it is input CCD14.
CCD14/
N18
I/O/Z
DVDD18
In 16-bit YCbCr mode, it is time multiplexed between CB6 and CR6 inputs.
UART_TXD2
In 8-bit YCbCr mode, it is time multiplexed between Y6, CB6, and CR6 of the upper
8-bit channel.
This pin is multiplexed between the CCDC and UART2. When used by the CCDC as
input CI5, it supports several modes.
CI5/
IPD
In 16-bit CCD AFE mode, it is input CCD13.
CCD13/
N17
I/O/Z
DVDD18
In 16-bit YCbCr mode, it is time multiplexed between CB5 and CR5 inputs.
UART_CTS2
In 8-bit YCbCr mode, it is time multiplexed between Y5, CB5, and CR5 of the upper
8-bit channel.
This pin is multiplexed between the CCDC and UART2. When used by the CCDC as
input CI4, it supports several modes.
CI4/
IPD
In 16-bit CCD AFE mode, it is input CCD12.
CCD12/
N16
I/O/Z
DVDD18
In 16-bit YCbCr mode, it is time multiplexed between CB4 and CR4 inputs.
UART_RTS2
In 8-bit YCbCr mode, it is time multiplexed between Y4, CB4, and CR4 of the upper
8-bit channel.
This pin is CCDC input CI3 and it supports several modes. In 16-bit CCD AFE
mode, it is input CCD11.
CI3/
IPD
N15
I
In 16-bit YCbCr mode, it is time multiplexed between CB3 and CR3 inputs.
CCD11
DVDD18
In 8-bit YCbCr mode, it is time multiplexed between Y3, CB3, and CR3 of the upper
8-bit channel.
This pin is CCDC input CI2 and it supports several modes. In 16-bit CCD AFE
mode, it is input CCD10.
CI2/
IPD
M17
I
In 16-bit YCbCr mode, it is time multiplexed between CB2 and CR2 inputs.
CCD10
DVDD18
In 8-bit YCbCr mode, it is time multiplexed between Y2, CB2, and CR2 of the upper
8-bit channel.
This pin is CCDC input CI1 and it supports several modes.
In 16-bit CCD AFE mode, it is input CCD9.
CI1/
IPD
M16
I
In 16-bit YCbCr mode, it is time multiplexed between CB1 and CR1 inputs.
CCD9
DVDD18
In 8-bit YCbCr mode, it is time multiplexed between Y1, CB1, and CR1 of the upper
8-bit channel.
This pin is CCDC input CI0 and it supports several modes.
In 16-bit CCD AFE mode, it is input CCD8.
CI0/
IPD
M15
I
In 16-bit YCbCr mode, it is time multiplexed between CB0 and CR0 inputs.
CCD8
DVDD18
In 8-bit YCbCr mode, it is time multiplexed between Y0, CB0, and CR0 of the upper
8-bit channel.
This pin is CCDC input YI7 and it supports several modes.
In 16-bit CCD AFE mode, it is input CCD7.
YI7/
IPD
L18
I
In 16-bit YCbCr mode, it is input Y7.
CCD7
DVDD18
In 8-bit YCbCr mode, it is time multiplexed between Y7, CB7, and CR7 of the lower
8-bit channel.
(1)
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2)
IPD = Internal pulldown, IPU = Internal pullup. (To pull up a signal to the opposite supply rail, a 1-k
Ω resistor should be used.)
(3)
Specifies the operating I/O supply voltage for each signal
42
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