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TNETV6446AINZWT 数据表(PDF) 19 Page - Texas Instruments |
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TNETV6446AINZWT 数据表(HTML) 19 Page - Texas Instruments |
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19 / 227 page  TMS320DM6446 www.ti.com SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010 Table 2-2. C64x+ Cache Registers (continued) HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION 0x0184 4030 L1DWIBAR L1D writeback invalidate base address register 0x0184 4034 L1DWIWC L1D writeback invalidate word count register 0x0184 4038 - Reserved 0x0184 4040 L1DWBAR L1D Block Writeback 0x0184 4044 L1DWWC L1D Block Writeback 0x0184 4048 L1DIBAR L1D invalidate base address register 0x0184 404C L1DIWC L1D invalidate word count register 0x0184 4050 - 0x0184 4FFF - Reserved 0x0184 5000 L2WB L2 writeback all register 0x0184 5004 L2WBINV L2 writeback invalidate all register 0x0184 5008 L2INV L2 Global Invalidate without writeback 0x0184 500C - 0x0184 5027 - Reserved 0x0184 5028 L1PINV L1P Global Invalidate 0x0184 502C - 0x0184 5039 - Reserved 0x0184 5040 L1DWB L1D Global Writeback 0x0184 5044 L1DWBINV L1D Global Writeback with Invalidate 0x0184 5048 L1DINV L1D Global Invalidate without writeback 0x0184 8000 - 0x0184 8004 MAR0 - MAR1 Reserved 0x0000 0000 - 0x01FF FFFF 0x0184 8008 - 0x0184 8024 MAR2 - MAR9 Memory Attribute Registers for EMIFA 0x0200 0000 - 0x09FF FFFF 0x0184 8028 - 0x0184 802C MAR10 - MAR11 Reserved 0x0A00 0000 - 0x0BFF FFFF 0x0184 8030 - 0x0184 803C MAR12 - MAR15 Memory Attribute Registers for VLYNQ 0x0C00 0000 - 0x0FFF FFFF 0x0184 8040 - 0x0184 8104 MAR16 - MAR65 Reserved 0x1000 0000 - 0x41FF FFFF Memory Attribute Registers for EMIFA/VLYNQ Shadow 0x4200 0000 - 0x0184 8108 - 0x0184 813C MAR66 - MAR79 0x4FFF FFFF 0x0184 8140- 0x0184 81FC MAR80 - MAR127 Reserved 0x5000 0000 - 0x7FFF FFFF 0x0184 8200 - 0x0184 823C MAR128 - MAR143 Memory Attribute Registers for DDR2 0x8000 0000 - 0x8FFF FFFF 0x0184 8240 - 0x0184 83FC MAR144 - MAR255 Reserved 0x9000 0000 - 0xFFFF FFFF 2.4.3 Peripherals The DSP has controllability for the following peripherals: • VICP • EDMA3 • ASP • 2 Timers (Timer 0 and Timer1) that can each be configured as 1 64-bit or 2 32-bit timers 2.4.4 DSP Interrupt Controller The DSP Interrupt Controller accepts device interrupts and appropriately maps them to the DSP’s available interrupts. The DSP Interrupt Controller is briefly described in Section 6.7, Interrupts, of this document. For more detailed on the DSP Interrupt Controller, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732). 2.5 Memory Map Summary Table 2-3 shows the memory map address ranges of the device. Table 2-4 depicts the expanded map of the Configuration Space (0x0180 0000 through 0x0FFF FFFF). The device has multiple on-chip memories associated with its two processors and various subsystems. To help simplify software development a unified memory map is used where possible to maintain a consistent view of device resources across all bus masters. Copyright © 2005–2010, Texas Instruments Incorporated Device Overview 19 Submit Documentation Feedback Product Folder Link(s): TMS320DM6446 |
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